Texas Instruments 3 Series Manual page 68

High accuracy battery monitor and protector for li-ion, li-polymer, and lifepo4 battery packs
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BQ76952
SLUSE13A – JANUARY 2020 – REVISED MAY 2021
16.2.1 Design Requirements (Example)
DESIGN PARAMETER
Minimum system operating voltage
Cell minimum operating voltage
Series cell count
Sense resistor
Number of thermistors
Charge voltage
Maximum charge current
Peak discharge current
Configuration settings
Protection subsystem configuration
OV protection threshold
OV protection delay
OV protection recovery hysteresis
UV protection threshold
UV protection delay
UV protection recovery hysteresis
SCD protection threshold
SCD protection delay
OCD1 protection threshold
OCD1 protection delay
OCD2 protection threshold
OCD2 protection delay
OCD3 protection threshold
OCD3 protection delay
OCC protection threshold
OCC protection delay
OTD protection threshold
OTD protection delay
OTC protection threshold
OTC protection delay
UTD protection threshold
UTD protection delay
UTC protection threshold
UTC protection delay
Host watchdog timeout protection delay
CFETOFF pin functionality
DFETOFF pin functionality
ALERT pin functionality
REG1 LDO Usage
Cell balancing
16.2.2 Detailed Design Procedure
Determine the number of series cells.
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Table 16-1. BQ76952 Design Requirements
3 (using TS1, TS2, and TS3 pins, all for cells)
programmed in OTP during customer production
Series FET configuration, device monitors, disables FETs upon fault, recovers autonomously
80 mV (corresponding to a nominal 80 A, based on a 1-mΩ sense resistor)
68 mV (corresponding to a nominal 68 A, based on a 1-mΩ sense resistor)
56 mV (corresponding to a nominal 56 A, based on a 1-mΩ sense resistor)
28 mV (corresponding to a nominal 28 A, based on a 1-mΩ sense resistor)
8 mV (corresponding to a nominal 8 A, based on a 1-mΩ sense resistor)
Use as CFETOFF, polarity = normally high, driven low to disable FET
Use as DFETOFF, polarity = normally high, driven low to disable FET
Use as ALERT interrupt pin, polarity = driven low when active, hi-Z otherwise
Enabled when imbalance exceeds 100 mV
Product Folder Links:
EXAMPLE VALUE
40 V
2.5 V
16
1 mΩ
68 V
8.0 A
20.0 A
4.30 V
500 ms
100 mV
2.5 V
20 ms
100 mV
50 µs
10 ms
80 ms
160 ms
160 ms
60°C
2 s
45°C
2 s
–20°C
10 s
0°C
5 s
5 s
Use for 3.3-V output
Copyright © 2021 Texas Instruments Incorporated
BQ76952
www.ti.com

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