Digital Interface; Default Jumper Settings - Texas Instruments ADS7043EVM-PDK User Manual

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Digital Interface

The ADS7043 digital output is available in SPI-compatible format, which makes interfacing with
microprocessors, digital signal processors (DSPs) and FPGAs easy. The ADS7043EVM offers 50-Ω
resistors between the SPI signals and edge connector J1 to aid with signal integrity. Typically, in high-
speed SPI communication, fast signal edges can cause overshoot; these resistors slow down the signal
edges in order to minimize signal overshoot.
The ADS7043EVM has clearly marked test points for all the SPI signals to allow observation of the
interface signals using an oscilloscope.
5 ADS7043EVM-PDK Initial Setup
This section presents the steps required to set up the ADS7043EVM-PDK kit before operation.
5.1

Default Jumper Settings

A silkscreen plot detailing the default jumper settings is shown in
Table 5 explains the configuration for these jumpers.
Reference Default
Designator Position
J2 Open
J4 Open
J5 Closed
J11 Closed
SBAU241 – November 2014
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Figure 2. ADS7043EVM Default Jumper Settings
Table 5. Default Jumper Configurations
Description
Alternate location to provide the negative input of the differential signal
Unassembled, by default
Point to insert an ammeter to measure VDD_ADC current, if required
Point to insert an ammeter to measure VDD_OPA current, if required
Copyright © 2014, Texas Instruments Incorporated
Figure 2.
ADS7043EVM-PDK
Digital Interface
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