Xilinx VC707 Manual page 5

VC707 BIST Design Description
Block Design IP
– Processor and Subsystems: MicroBlaze, MicroBlaze Debug Module (MDM),
Local Memory Bus, LMB BRAM Controller, Block Memory Generator, Proc Sys
Reset, AXI Interrupt Controller
– AXI Bus: AXI Interconnect, AXI Timer
– Memory: AXI BRAM Controller, MIG 7 Series, AXI DMA
– Peripherals: AXI USB2, AXI Ethernet, AXI EMC, AXI IIC, AXI GPIO, AXI UART
16550, XADC Wizard
– Other IP: Constant, Concat, gte2_top
• Vivado Design Suite Tcl Command Reference Guide
• Designing IP Subsystems Using IP Integrator
Note: Presentation applies to the VC707
(UG835)
(UG994)