Table of Contents
Advertisement
Register
Address
D3
D2
CLKCHG OSCC
FF00H
R/W
VADSEL VDSEL
FF01H
R/W
SVDS3 SVDS2 SVDS1 SVDS0
FF04H
R/W
0
0
SVDDT SVDON
FF05H
R
FOUTE
0
FOFQ1 FOFQ0
FF06H
R/W
R
0
0
WDEN WDRST
FF07H
R
SIK03
SIK02
SIK01
FF20H
R/W
K03
K02
FF21H
R
KCP03 KCP02 KCP01 KCP00
FF22H
R/W
SIK13
SIK12
SIK11
FF24H
R/W
K13
K12
FF25H
R
KCP13 KCP12 KCP11 KCP10
FF26H
R/W
0
0
FF28H
R
Remarks
∗1 Initial value at initial reset
∗2 Not set in the circuit
∗3 Constantly "0" when being read
S1C63358 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (a) I/O memory map (FF00H–FF28H)
∗1
D1
D0
Name Init
CLKCHG
0
0
VDC
OSCC
0
∗3
∗2
0
–
R
R/W
VDC
0
VADSEL
0
0
0
VDSEL
0
∗3
∗2
0
–
R
∗3
∗2
0
–
SVDS3
0
SVDS2
0
SVDS1
0
SVDS0
0
∗3
∗2
0
–
∗3
∗2
0
–
SVDDT
0
R/W
SVDON
0
FOUTE
0
∗3
∗2
0
–
FOFQ1
0
R/W
FOFQ0
0
∗3
∗2
0
–
∗3
∗2
0
–
WDEN
1
R/W
W
∗3
WDRST
Reset
SIK03
0
SIK00
SIK02
0
SIK01
0
SIK00
0
∗2
K03
–
K01
K00
∗2
K02
–
∗2
K01
–
∗2
K00
–
KCP03
1
KCP02
1
KCP01
1
KCP00
1
SIK13
0
SIK10
SIK12
0
SIK11
0
SIK10
0
∗2
K13
–
K11
K10
∗2
K12
–
∗2
K11
–
∗2
K10
–
KCP13
1
KCP12
1
KCP11
1
KCP10
1
∗3
∗2
0
–
0
SIK20
∗3
∗2
0
–
∗3
∗2
0
–
R/W
SIK20
0
1
0
OSC3
OSC1
CPU clock switch
On
Off
OSC3 oscillation On/Off
Unused
2.25 V
1.35 V
CPU operating voltage switch (1.35 V: OSC1, 2.25 V: OSC3)
V
V
Power source selection for A/D converter
C2
DD
V
V
Power supply selection for oscillation system voltage regulator
C2
DD
Unused
Unused
SVD criteria voltage setting
[SVDS3–0]
Voltage(V)
1.05
[SVDS3–0]
1.95
Voltage(V)
Unused
Unused
Low
Normal
SVD evaluation data
On
Off
SVD circuit On/Off
Enable Disable FOUT output enable
Unused
FOUT
frequency
selection
Unused
Unused
Enable
Disable
Watchdog timer enable
Reset
Invalid
Watchdog timer reset (writing)
Enable
Disable
Enable
Disable
K00–K03 interrupt selection register
Enable
Disable
Enable
Disable
High
Low
High
Low
K00–K03 input port data
High
Low
High
Low
K00–K03 input comparison register
Enable
Disable
Enable
Disable
K10–K13 interrupt selection register
Enable
Disable
Enable
Disable
High
Low
High
Low
K10–K13 input port data
High
Low
High
Low
K10–K13 input comparison register
Unused
Unused
Unused
Enable Disable
K20 interrupt selection register
EPSON
Comment
0
1
2
3
4
1.10
1.15
1.20
1.25
1.30
8
9
10
11
12
13
2.00
2.05
2.10
2.20
2.30
[FOFQ1, 0]
0
1
Frequency
f
/64
f
OSC1
OSC1
5
6
7
1.40
1.60
14
15
2.50
2.60
2
3
/8
f
f
OSC1
OSC3
17
Advertisement
Table of Contents
