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Chapter 4 Programming
Address List of Involved Registers
MBAR
RSR
SYPCR
MCR
PLLCR
CDVCR
CLKOCR
PEPAR
GMR
AVR
BR0
OR0
BR1
OR1
BR2
OR2
BR3
OR3
BR4
OR4
BR5
OR5
BR6
OR6
BR7
OR7
CICR
SDCR
VCSR
BCSR
4.3 Initializing the Cache
Before the system enables any cache present, they should be invalidated using:
cinva bc
Furthermore, the complete address range should not be cachable, as caching only makes sense on
DRAM and FLASH EPROM. Other areas should never be cached and must be switched to serialized in
order to prevent the MC68040/MC68060 from mixing up read and write cycles.
The easiest way of doing this is to make use of the DTT0 register, in the following way:
move.l
movec
The code above sets all addresses below $80000000 to cacheable and non-serialized, whereas all
addresses above are set to non-cacheable and serialized.
July 19,1997
0x3FF00
0xC0001009
0xC0001022
0xC0001000
0xC0001010
0xC0001014
0xC000100C
0xC0001016
0xC0001040
0xC0001008
0xC0001050
0xC0001054
0xC0001060
0xC0001064
0xC0001070
0xC0001074
0xC0001080
0xC0001084
0xC0001090
0xC0001094
0xC00010A0
0xC00010A4
0xC00010B0
0xC00010B4
0xC00010C0
0xC00010C4
0xC0001540
0xC000151E
0xCD000005
0xCD000007
#$807FE040,d1
d1,dtt0
© PEP Modular Computers
(CPU space!)
VM162/VM172
Page 4- 7
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