Table of Contents
Advertisement
Chapter 2 Functional Description
2.5.5 VME Control/Status Register
The VME Control/Status Register is a one byte wide register with read/write access at default address
CD 00 00 05 (HEX).
7
P_IRQ5
CS7 + $5
Note: All bits except bit 4 (First Slot Detection) are cleared after reset. The firmware of the board initia-
lizes some of them at startup according to the default parameters stored in the EEPROM.
Register Description
Name
Value
P_IRQ5
1
bit 7
EN_DPR
1
bit 6
EN_BERR2
1
bit 5
FSD
1
bit 4
BADR3 -
BADR0
bits 3-0
Note: All bits are cleared during a reset. FSD is set dependent on the slot position of the board in the
system. The board's firmware initializes EN_DTR, EN_BERR2 and BADR[3-0] during startup follo-
wing default parameters stored in the serial EEPROM.
Juli 23, 1997
6
5
EN_DPR
EN_BERR2
Reset (HW)
Reset PEP (SW)
Slot 1
Other
Slot 1
0
0
0
0
0
Value stored in
EEPROM
0
0
1
1
0
1
0
0
Value stored in
EEPROM
© PEP Modular Computers
4
3
FSD
BADR3
BADR2
Description
Other
0
Pending mailbox IRQ
Dual-port RAM (inc. mailbox IRQ) for
VME requester enabled. Base address
fixed using BADRx bits
0
Enable bus monitor timer, all VME
cycles, timeout after 128µs
0
VMEbus 'First Slot Detection' flag,
system controller
VME address location of dual-ported
RAM. Equivalent to VME address lines
A23-A20, programmable from $0-$F in
1 MByte windows, enabled with
EN_DPR
VM162/VM172
2
1
0
BADR1
BADR0
Page 2- 13
Advertisement
Table of Contents
