Table of Contents
Advertisement
VM162/VM172
4.2 Initializing the 68EN360
Many components of the VM62(A) / VM42(A) are controlled by the MC68EN360. Due to this fact, this
chip requires a special initialization sequence before any other software can be started.
The following list describes how the initialization must be performed on the VM62(A) / VM42(A).
Note: The order of the initialization listed below must not be changed, otherwise erratic behaviour of
the board may result.
1) Set DPRBASE to 0x000000
Example
move.l
move.l
movec
moves.l
2) Clear reset status register
3) Set system protection register
• bus monitor enabled, 128 system clocks timeout
4) Set module configuration register
• bus request MC68040 arbitration ID: 3
• arbitration synchronous timing mode
• bus clear out arbitration ID: 3
• SIM60 registers are Supervisor Data
• BusClear in arbitration ID: 3
• interrupt arbitration: 3
5) Set PLL enabled and lock access
6) Lock access to clock divider control register
7) Configure CLK lines
• COM2 to full strength
• COM1 disabled
• register access locked
Page 4- 4
#7,d1
select CPU space
#$7000001,d0
value to write to MBAR
d1,dfc
select CPU space
d0,MBAR
set MBAR
© PEP Modular Computers
Chapter 4 Programming
0x7000001.L -> MBAR (in CPU space!)
0xFF.B -> RSR
0x7.B -> SYPCR
0x60008CB3.L -> MCR
0xC000.W -> PLLCR
0x8000.W -> CDVCR
0x83.B -> CLKOCR
July 19, 1997
Advertisement
Table of Contents
