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VM162/VM172
2.6.3 Bus Timer
The VM162/VM172 provides an 128µs timeout timer which monitors the cycle lengths of on-board
data transfers, including on-board I/O, CXC, IndustryPack, dual-ported SRAM and some VME. After a
timeout occurs, it generates an on-board BERR signal for error termination.
This timer is enabled / disabled via the Board Control/Status Register, which also supplies a timeout sta-
tus bit in order to identify bus errors generated by the on-board bus error timer.
Note: During VMEbus cycles, the on-board bus error timer is reset as soon as the VM162/VM172 gains
VMEbus ownership. This means that the time gap between a VMEbus request and the start of a VMEbus
cycle is monitored by the on-board Bus Timer. VMEbus cycles themselves are monitored by the separate
VME Bus Monitor.
2.6.4 Watchdog Timer
A 512ms watchdog timer is also provided by the VM162/VM172. Once enabled via the Board Control/
Status Register, the watchdog timer cannot be reset by software. It must be re-triggered via the corre-
sponding bit in the Board Control/Status Register periodically within the timeout period.
'Watchdog timer running' is a status that is displayed by the yellow front panel LED. At timeout, the
watchdog timer triggers the on-board system reset.
Note: If the board's VME SYSRES* jumper is set, the watchdog timer can reset the whole of the VME
system.
2.6.5 Board Control/Status Register
The Board Control/Status Register is a one byte wide register with read/write access at default address
CD 00 00 07 (HEX).
7
WDG
CS7 + $7
Note: Information may be lost if the user writes to bit 7.
Page 2- 16
6
5
BERR2
BERR1
EN_WDG
© PEP Modular Computers
Chapter 2 Functional Description
4
3
2
TR_WDG
EN_BERR1
1
0
ACFAIL
LED_G
Juli 23, 1997
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