Vme Slave Interface - PEP VM162 User Manual

Chapter 2 Functional Description
2.5.2.3 SYSRES* Generator
The VM162/VM172 contains a power monitor which generates on-board system reset signal after the
on-board voltage falls below 4.65 V. This on-board system reset can also drive VME SYSRES*. If the
VM162/VM172 is not intended to drive VME SYSRES*, the signal can be disconnected using a jumper.
Note: In contrast to SYSCLK*, which may be driven by one board in the system, SYSRES* may be
driven more than once in a system.
SYSRES* originating from another power monitor within the system always resets the VM162/VM172.
2.5.2.4 VMEbus Monitor
The VM162/VM172 also provides a bus monitor for the VMEbus. A 128 µs timeout timer monitors
VMEbus data transfer cycle lengths and generates a VMEbus BERR* signal for error termination. This
timer is enabled/disabled via the VME Control/Status Register, which also supplies a timeout status bit
in order to identify bus errors generated by the VMEbus monitor.

2.5.3 VME Slave Interface

2.5.3.1 Dual-Ported RAM
The VM162/VM172 provides 256 kByte or 1 MByte of on-board SRAM which is dual-ported between
the CPU and VMEbus. Read-Modify-Write cycles (TAS instruction used for semaphores) are supported
in any direction.
The location of the dual ported SRAM as seen from VME is programmable via the VME Control/Status
Register. There are 16 different base addresses possible with separate enable/disable functions all loca-
ted in VME A23/D16 space.
Note: The lowest 8 kByte of the dual-ported SRAM is reserved for generating mailbox interrupts.
2.5.3.2 Mailbox Interrupt
An external VMEbus master may interrupt the VM162/VM172 by setting the corresponding mailbox in-
terrupt bit. This bit called P_IRQ5 is placed within the VME Control/Status Register. Setting this bit ge-
nerates an autovectored 5 interrupt on the CPU. Typically, the on-board CPU resets P_IRQ5 during
processing the corresponding interrupt service routine.
Notes:
The complete VME Control/Status Register can be read also from an external VMEbus Master. It is
addressed on every odd address of the lowest 8 kByte block of the VME board address. Only the mailbox
interrupt P_IRQ5 can, however, be set; all other bits are write protected from the VME.
As the P_IRQ5 bit is located at bit 7 of the register, it can be directly used as a semaphore due to the fact
that Read-Modify-Write access is supported.
Although the VM162/VM172 cannot access itself via the VMEbus, setting the mailbox interrupt bit on
the local side also generates the interrupt to the CPU.
Juli 23, 1997 © PEP Modular Computers
VM162/VM172
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