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Chapter 2 Functional Description
Table 2.2: DRAM/FLASH Options
Note: DRAM is accessed with a 5-2-2-2 burst cycle at 25 MHz bus clock (68060/50MHz) and with a 6-
2-2-2 burst cycle at 33 MHz bus clock (68040(V)/33MHz).
2.3.2 SRAM
The SRAM on the VM162/VM172 is organized in one bank with 16 bit wide data access bus. It is bak-
ked by two onboard service-free GoldCaps and optionally via VME StandBy. Additionally, this me-
mory is dual-ported. Users of the VMEbus and the onboard CPU both have access to this memory.
The dual-ported SRAM is soldered directly on the base board available with size of 256 kB or 1 MB.
2.3.3 Boot ROM (optional)
The VM162/VM172 Boot ROM is an optional socket device. The sockets support devices up to 512 kB
size with a 16 bit wide data access for PLCC EPROMs.
By default, the board's firmware is stored directly in the FLASH on memory piggyback. Thus, the Boot
ROM is not mandatory. In case of using a Memory-PB without FLASH or if an application requires the
board's firmware to be separated from FLASH then the Boot ROM socket can be used. Whether starting
from FLASH or from Boot ROM is selected by jumper.
Supported chips for the Boot ROM:
128Kx8, 256Kx8, 512Kx8 PROM or EPROM, Standard JEDEC Pinning
Juli 23, 1997
Name
DRAM Size
DM600
4 MByte
DM601
16 MByte
DM602
1 MByte
DM603
32 MByte
DM604
8 MBytes
© PEP Modular Computers
VM162/VM172
FLASH Size
1 or 4 MByte
1 or 4 MByte
0 or 0.5 or 2 MByte
1 or 4 MByte
1 or 4 MBytes
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