Board Control Logic; Boot Decoder Logic; Interrupt Control - PEP VM162 User Manual

Vmebus single-board computer with dual industrypack support

Table of Contents

VM162/VM172

2.6 Board Control Logic

The VM162/VM172 gives the user the choice to execute startup procedures from three different me-

mory areas. These are FLASH (default on the memory Piggyback), or the optional Boot ROM or me-

mory on the VMEbus. The boot device/memory is selected by jumpers.

The boot decoder logic redirects the initial CPU access which is always starting at address 0 (HEX) to

the boot device according the boot jumper setting. The boot device is swiched automatically to its de-

fault address area after the ﬁrst access on it with its default address.

For more details, please refer to the Programming Chapter in this manual.

Notes: If VMEbus memory is selected to be the default boot device, it must be located at VME base

address 0 (HEX) in A24/D16 address space for supervisory program/data access (AM codes 3E, 3D).

If FLASH or VMEbus memory is selected to be the boot device, the optional Boot ROM can be used as

a standard ROM for storing program, data or application speciﬁc parameters.

The interrupt control logic processes internal interrupt requests (68EN360), together with external re-

quests (VME) and external autovectored interrupt requests. The interrupt control logic is built up using

the 68EN360 internal interrupt controller for QUICC internal 68EN360 and a seven level VMEbus in-

terrupt handler with the corresponding mask register.

2.6.2.1 Internal Requests

Internal requests are related to all interrupt requests caused by the 68EN360 sources, including the

68EN360 system integration functions (watchdog timer, periodic interrupt timer) and the communica-

tion processor module (RISC controller, timers, DMAs, SCCs and so on). For more information, please

refer to the 68EN360 User's Manual.

In order to avoid conﬂicts regarding interrupt levels, it is recommended to use IRQ level 4 for 68EN360

CPU internal requests and IRQ level 6 for 68EN360 SIM60 internal requests.

Note: The four IRQ lines speciﬁed by CXC are supplied by the 68EN360 Port C lines and are, therefore,

also processed as internal requests (PC0, 1, 2, 3).

Page 2- 14

Chapter 2 Functional Description

Juli 23, 1997

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Vm172