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PEP VM162 User Manual

Vmebus single-board computer with dual industrypack support
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VM162/VM172
VMEbus Single-Board Computer with
Dual IndustryPack Support
Manual Order Nr. 16596
User's Manual
Issue 1
®

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Summary of Contents for PEP VM162

  • Page 1 VM162/VM172 VMEbus Single-Board Computer with Dual IndustryPack Support Manual Order Nr. 16596 User’s Manual Issue 1 ®...

  • Page 3: Table Of Contents

    1.8 Related Publications ..............1-11 1.9 Schematic Board Layout............. 1-12 Chapter Chapter Functional Description............2-1 2.1 VM162/VM172 Block Diagram ............ 2-3 2.2 CPU Options................. 2-4 2.3 Memory ..................2-4 2.3.1 DRAM/FLASH ....................2-4 2.3.2 SRAM ......................2-5 2.3.3 Boot ROM (optional) ..................2-5 2.3.4 EEPROM ......................
  • Page 4 3.2.3 Protective Ground - Signal Ground ............. 3-5 3.2.4 VME SYSRES*....................3-5 3.2.5 CXC Mode ....................3-6 3.3 Jumper Description (Solder Side)..........3-7 3.3.1 CPU Type ..................... 3-8 3.3.2 CPU Power Supply..................3-8 Page TOC- 2 © PEP Modular Computers Juli 23, 1997...
  • Page 5 3.3.8 SRAM Data Retention................. 3-10 3.3.9 BERR1 Timeout ..................3-10 3.3.10 Backup Current Test Bridge ..............3-10 Chapter Programming ............... 4-1 4.1 VM162/VM172 Address Map............4-3 4.2 Initializing the 68EN360............... 4-4 4.3 Initializing the Cache..............4-7 Appendices Memory Piggybacks SI6 Piggybacks...
  • Page 6 Table of Contents VM162/VM172 Page TOC- 4 © PEP Modular Computers Juli 23, 1997...
  • Page 7 VM162/VM172 Preface Juli 23, 1997 © PEP Modular Computers Page 0- 1...
  • Page 8 Preface Unpacking and Special Handling Instructions This PEP product is carefully designed for a long and fault-free life; nonetheless, its life expectancy can be drastically reduced by improper treatment during unpacking and installation. Observe standard anti-static precautions when changing piggybacks, ROM devices, jumper settings etc. If the product contains batteries for RTC or memory back-up, ensure that the board is not placed on conductive surfaces, including anti-static plastics or sponges.
  • Page 9 This document contains proprietary information of PEP Modular Computers. It may not be copied or transmitted by any means, passed to others, or stored in any retrieval system or media, without the prior consent of PEP Modular Computers or its authorized agents.
  • Page 10 In the event of repair, refund, or replacement of any part, the ownership of the removed or replaced parts reverts to PEP Modular Computers, and the remaining part of the original guarantee, or any new guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired items.

  • Page 11: Introduction

    1.3 Controller eXtension Connector ........... 1-4 1.4 Front Panel and I/O Configuration ..........1-4 1.5 Features..................1-6 1.6 Specifications ................1-8 1.7 Ordering Information..............1-10 1.8 Related Publications ..............1-11 1.9 Schematic Board Layout ............. 1-12 Juli 23, 1997 © PEP Modular Computers Page 1- 1...
  • Page 12 VM162/VM172 Chapter 1 Introduction Page 1- 2 © PEP Modular Computers Juli 23, 1997...

  • Page 13: Product Overview

    WAN interfaces provided, communicational versatility is guaranteed. Two on-board EPROM sockets are designed to accommodated ROMed applications and/or the PEPbug debug monitor.The VM162/172 is supplied with these sockets empty and the PEPbug programmed into the FLASH memory residing on one of the DM6xx memory piggybacks.

  • Page 14: Controller Extension Connector

    SCSI and fieldbus connection (PROFIBUS, CAN, LON and Bitbus). Hence, a fea- ture of the VM162/172 is that the ‘raw’ serial signals from the ‘QUICC’ SCC2, SCC3 and SCC4 chan- nels being internally wired to the front panel as well as to the CXC interface.
  • Page 15 Chapter 1 Introduction VM162/VM172 SC and SI6 piggybacks adapt the multi-protocol serial channels of the ‘QUICC’ to the physical inter- faces provided on the VM162/172’s front-panel and CXC: SCC1 channel supports: SI6-10B5 Ethernet 10base5 (AUI) SI6-10B2 Ethernet 10base2 (Thin) SI6-10BT...

  • Page 16: Features

    Interfaces CXC Interface CXC Interface The 96-pin interface allows other I/O possibilities to be realised by utilising PEP’s plug-in cards such as the CXM-PFB12, CXM-CAN, CXM-LON, CXM-SCSI or CXM-SIO3.. Ethernet Interface Three different SI6 piggybacks complete with all the associated control logic are available providing 10Base2, 10Base5 or 10BaseT interfaces.
  • Page 17 This is a dual-ported battery-backed (Goldcap) memory area with a 16 bit- wide access bus. Users of the VMEbus and CPU both have access to this memory. EEPROM A 2 kbit EEPROM is provided on-board, 1 kbit has been pre-programmed with PEP production data lea- ving the remaining available space for user application code. Juli 23, 1997 ©...

  • Page 18: Specifications

    16 software selectable base addresses Two card holders with I/O ported to 50-pin flat-band IndustryPack Interface cable or D-Sub connector on front-panel CXC Interface DIN 41612 (C), 96-pin, 3 NMSI ports, DMA Page 1- 8 © PEP Modular Computers Juli 23, 1997...
  • Page 19 SI6-xx piggybacks Serial Interface from MC68EN360 (ports SCC2, SC-Interface SCC3 and SCC4) with standard RS232 configuration ≈ 6.5W @ 50 MHz VM162 w/ MC68060 Power Consumption ≈ 8.5W @ 33 MHz VM172 w/ MC68040 0ºC to +70ºC (standard) Temperature -40ºC to +85ºC (extended / storage)

  • Page 20: Ordering Information

    11855 memory for VM162/172 Memory Piggyback with 1 MByte DRAM and 1 MByte FLASH DM 602 12765 memory for the VM162/172 Memory Piggyback with 32 MByte DRAM and 512 kByte FLASH DM 603 13027 memory for the VM162/172 Memory Piggyback with 32 MByte DRAM and 2 MByte FLASH...

  • Page 21: Related Publications

    15191 (male) for terminal connection Important : The VM162 and VM172 must be ordered with a memory module (DM60x) and a front-pa- nel with integrated SI6-piggyback module. For configurations requiring the 2 x 50-pin D-Sub front-panel connectors instead of the flat-band cable option, please contact the nearest PEP sales office for further information.

  • Page 22: Schematic Board Layout

    VM162/VM172 Chapter 1 Introduction 1.9 Schematic Board Layout Page 1- 12 © PEP Modular Computers Juli 23, 1997...

  • Page 23: Functional Description

    VM162/VM172 Chapter Functional Description 2.1 VM162/VM172 Block Diagram............. 2-3 2.2 CPU Options ................. 2-4 2.3 Memory..................2-4 2.3.1 DRAM/FLASH....................2-4 2.3.2 SRAM......................2-5 2.3.3 Boot ROM (optional)..................2-5 2.3.4 EEPROM.......................2-6 2.4 Communication Controller 68EN360 (QUICC) ......2-6 2.4.1 Use of 68EN360 Communication Ports ............2-6 2.4.2 Use of 68EN360 Memory Controller ............2-7 2.4.3 Use of 68EN360 Interrupt Controller ............2-7...
  • Page 24 2.10.8 IP Memory Size Control ................2-32 2.10.9 IP Interface Address Map ................. 2-32 2.10.10 Interrupt Control Register ..............2-33 2.10.11 Slot Control Register ................2-34 2.10.12 Connectors ....................2-35 Page 2- 2 © PEP Modular Computers Juli 23, 1997...

  • Page 25: Vm162/Vm172 Block Diagram

    Chapter 2 Functional Description VM162/VM172 2.1 VM162/VM172 Block Diagram Juli 23, 1997 © PEP Modular Computers Page 2- 3...

  • Page 26: Cpu Options

    Memory Management Unit (MMU) and Floating Point Unit (FPU). There are three categories of VM162/VM172 CPU boards. At the top there is the 68060 CPU board which offers 2 to 3 times performance of a the following 68040 CPU board. At the low end there is the CPU 68040V board which is the low cost and also low power version.

  • Page 27: Sram

    2-2-2 burst cycle at 33 MHz bus clock (68040(V)/33MHz). 2.3.2 SRAM The SRAM on the VM162/VM172 is organized in one bank with 16 bit wide data access bus. It is bak- ked by two onboard service-free GoldCaps and optionally via VME StandBy. Additionally, this me- mory is dual-ported.

  • Page 28: Eeprom

    The 68EN360 provides 5 serial ports based on 4 SCCs and 1 SMCs. These multiprotocol serial ports can be physically translated to the different standards due to application specific demands. This translation is very flexible on the VM162/VM172 by using SI- and SC- piggybacks or even CXMs. 5 configured serial ports are available at front panel connectors.

  • Page 29: Use Of 68En360 Memory Controller

    2.4.2 Use of 68EN360 Memory Controller Beside its main purpose which is to provide communication power to the VM162/VM172 the I/O con- troller 68EN360 is also used for some system integration function. First of all this is DRAM control and global memory decoding.

  • Page 30: Use Of 68En360 Dma Channels

    Programming Chapter must be closely adhered to. 2.5 VMEbus Interface The VM162/VM172 has a complete VMEbus Master interface with arbiter, system clock driver, power monitor with system reset driver, IACK daisy chain driver and a 7-level VMEbus interrupt handler.

  • Page 31: Vme Master Interface

    2.5.1 VME Master Interface 2.5.1.1 Supported Data Transfer Types (VMEbus AM Codes) The VM162/VM172 supports three addressing modes which are A32, A24 and A16. The following AM codes according to the standard for VME64 are supported by the VM162/VM172. Table 2.5: External Signal Connection...

  • Page 32: System Controller Functions

    2.5.2 System Controller Functions 2.5.2.1 Automatic First-Slot Detection During power-up, the VM162/VM172 automatically detects if the board is placed in the far left slot of the system. If so, it acts automatically as the system controller. Note: This information is stored in the FSD (First Slot Detection) bit within the VMEbus Control/Status register.

  • Page 33: Vme Slave Interface

    4.65 V. This on-board system reset can also drive VME SYSRES*. If the VM162/VM172 is not intended to drive VME SYSRES*, the signal can be disconnected using a jumper. Note: In contrast to SYSCLK*, which may be driven by one board in the system, SYSRES* may be driven more than once in a system.

  • Page 34: Vme Address Map From The Vme Side

    Note: All of the possible board address ranges are located in VME A24/D16 addressing mode. It is en- abled for supervisor/user data access in accordance to AM codes 3D and 39. Page 2- 12 © PEP Modular Computers Juli 23, 1997...

  • Page 35: Vme Control/Status Register

    Note: All bits are cleared during a reset. FSD is set dependent on the slot position of the board in the system. The board’s firmware initializes EN_DTR, EN_BERR2 and BADR[3-0] during startup follo- wing default parameters stored in the serial EEPROM. Juli 23, 1997 © PEP Modular Computers Page 2- 13...

  • Page 36: Board Control Logic

    2.6 Board Control Logic 2.6.1 Boot Decoder Logic The VM162/VM172 gives the user the choice to execute startup procedures from three different me- mory areas. These are FLASH (default on the memory Piggyback), or the optional Boot ROM or me- mory on the VMEbus.
  • Page 37 Enable VME IRQ7 EN_IRQ6 Enable VME IRQ6 EN_IRQ5 Enable VME IRQ5 EN_IRQ4 Enable VME IRQ4 EN_IRQ3 Enable VME IRQ3 EN_IRQ2 Enable VME IRQ2 EN_IRQ1 Enable VME IRQ1 SYSFAIL Enable VME SYSFAIL IRQ Juli 23, 1997 © PEP Modular Computers Page 2- 15...

  • Page 38: Bus Timer

    Note: During VMEbus cycles, the on-board bus error timer is reset as soon as the VM162/VM172 gains VMEbus ownership. This means that the time gap between a VMEbus request and the start of a VMEbus cycle is monitored by the on-board Bus Timer.
  • Page 39 VME ACFAIL signal latched when active in order to bit 1 distinguish between a level 7 NMI from an ABORT or ACFAIL. LED_G Read/Write Enables the green ‘general purpose’ front panel LED. bit 0 Juli 23, 1997 © PEP Modular Computers Page 2- 17...

  • Page 40: Special Functions

    For more information on the EEPROM, please refer to the XICOR X25C02 data sheet. 2.7.3 TICK Timer The 68EN360 internal Periodic Interrupt Timer is used by the PEP supported real-time operating sy- stems as TICK generator. For more information, please refer to the 68EN360 User’s Manual.

  • Page 41: Data Retention For Rtc And Sram

    RTC (typical onboard backup current is 2 µA). Long term data retention is made via the VMEbus 5V Stby line. With respect to the VM162/VM172, this voltage can drop to 2.5V, with the typical current via the 5V Stby being 30µA at 3V.

  • Page 42: Serial Communication Ports

    Chapter 2 Functional Description 2.8 Serial Communication Ports The 5 serial ports of the VM162/VM172 are based on the 4 SCCs and 1 SMCs of the 68EN360. These multiprotocol serial ports can be physically translated to the different standards due to application spe- cific demands.

  • Page 43: Ethernet/Ser4 Port

    Fieldbus applications available as well as a standard RS232 in- terface. for more information, please refer to the SI Piggyback Appendix in this manual. Juli 23, 1997 © PEP Modular Computers Page 2- 21...

  • Page 44: Ser1, Ser2 And Ser3 Ports

    In addition, the signals of SCC2, SCC3 and SCC4 are routed to the CXC. This is mainly useful for phy- sical adaptions where the application requirements cannot be met using SC piggybacks. SER1, SER2 and SER3 Pinouts RJ45 Connector Signal Mini D-Sub Female Connector Signal N/C: Not Connected Page 2- 22 © PEP Modular Computers Juli 23, 1997...

  • Page 45: Term Pinouts

    The port based on the SMC is fixed to RS232 interfaces. This port supply RxD/TxD interfaces with soft- ware handshake (XON/XOFF) capability. Usually, this port is used as terminal/debug port. RJ45 Connector Signal Mini D-Sub Female Connector Signal N/C: Not Connected Juli 23, 1997 © PEP Modular Computers Page 2- 23...

  • Page 46: Cxc Interface

    PB14/_RTS3/_L1RQB/L1ST3 PB17/_RSTRT1/STRBI PC6/_CTS2 PC8/_CTS3/_L1TSYNCB/SDACK2 PC7/_CD2/_TGATE2 _CS-CXC (CS5 of 68360) PA12/CLK5/BRGO3TIN3 PC10/_CTS4/_L1TSYNCA/_SDACK1 PA13/CLK6/_TOUT3/L1RCLKB/BRGCLK2 PA5/TXD3/L1RXDB R/_W _SYSR PA4/RXD3/L1TXDB _UDS _LDS _EDTACK _CXC-CS2 16 MHz CLOCK _CXC-CS3 _CXC-CS4 _CXC-CS0 _CXC-CS5 _CXC-CS1 _CXC-CS6 _CXC-CS7 Page 2- 24 © PEP Modular Computers Juli 23, 1997...
  • Page 47 68302 HW 68(EN)360 Pin Nr. Comment Function Compatible Port DMA_ACK DMA_REQ 68302 HW 68(EN)360 Pin Nr. Comment Function Compatible Port SER1_RCLK SER1_TCLK PA10 SER1_TXD SER1_RXD SER1_RTS PB13 SER1_DTR PB17 SER1_CTS SER1_CD Juli 23, 1997 © PEP Modular Computers Page 2- 25...
  • Page 48 Not usable if SI-Module uses SCC4 See note 4 SER3_CTS PC10 Not usable if SI-Module uses SCC4 See note 4 SER3_CD PC11 Not usable if SI-Module uses SCC4 See note 4 Page 2- 26 © PEP Modular Computers Juli 23, 1997...
  • Page 49 2) On a standard VM162/VM172 board, these signals are used for SPI to which the EEPROM is already connected. PB0 is chip select of the EEPROM. 3) On PA13, a 24 MHz clock signal is routed via jumper J11. This signal is always needed for PEP standard software (serial drivers).
  • Page 50 The CXC ports SER1, SER2 and SER3 are equivalent to ports SCC2, SCC3 and SCC4 resp. on the 68xx360. With regard to special CXC capabilities, the CXC pinout on the VM162/VM172 has been developed to provide maximum compatibility between the standard CXC functions. In addition, all signals are availa- ble in order to configure 2 time division multiplexed channels via the CXC (ISDN, PCM, GCI and so...
  • Page 51 SPI slave (I) SPI Clock SPICLK Output clock from the SPI master (O); input clock to the SPI slave (I) SPI Select _SPISEL SPI slave select input (I) Juli 23, 1997 © PEP Modular Computers Page 2- 29...

  • Page 52: Industrypack (Ip) Interface

    The VM162/177 interface up to two IndustryPacks (IPs, referred as IPa and IPb). The implementation of the IP interfaces is according to the VITA-4 standard for IP modules. The VM162/177 (referred also as “IP-Carrier“ in this chapter) interfaces the two IP slots through a pro- grammable IP controller.

  • Page 53: Ip Interface Controller

    After a board reset the complete IP interrupt control logic is reset by default. That means the Interrupt Enable bit is cleared as well as the IRQ level bits ( BIT 2-0). Juli 23, 1997 © PEP Modular Computers Page 2- 31...

  • Page 54: Ip Memory Size Control

    Note: Whether 1 or 8 MByte memory address space is selected depends on the memory size bit within the IP slot control register. Depending on the memory size bit, the memory page bits are relevant or not. Default is 8 MByte, not paged. Page 2- 32 © PEP Modular Computers Juli 23, 1997...

  • Page 55: Ip Interrupt Control Register

    0 -> IP interrupt request on INT0 line disabled 1 -> IP interrupt request on INT0 line enabled INT0_IL2-0 IP IRQ level for INT0 line (2 or 4 or 6) Juli 23, 1997 © PEP Modular Computers Page 2- 33...

  • Page 56: Ip Slot Control Register

    1 ->IP RESET line not active, IP enabled M_SIZE 0 -> IP linear addressable mem space 8 MB 1 -> IP linear addressable mem space 1 MB M_PAG active memory page (1-of-8) 1 MB mem pages Page 2- 34 © PEP Modular Computers Juli 23, 1997...

  • Page 57: Ip Connectors

    VME Connector The figure above shows the position of IPa and IPb on the VM162/177. Each IP is plugged into the board via a pair of 50-pin IP connectors. The rear one (near to the VMEbus connector) connects the IP bus and control signals whereas the other one (near to the frontpanel) carries the IP I/O signals.
  • Page 58 VM162/VM172 Chapter 2 Functional Description 2.10.12.1 IP I/O Connector, Pinout Pin1 Pin25 Pin26 Pin50 2.10.12.2 IP I/O Flat Cable Connector, Pinout Pin2 Pin50 Pin49 Pin1 Page 2- 36 © PEP Modular Computers Juli 23, 1997...
  • Page 59 Chapter 2 Functional Description VM162/VM172 2.10.12.3 IP I/O DSUB Frontpanel Connector, Pinout Pin50 Pin25 Pin1 Pin26 Juli 23, 1997 © PEP Modular Computers Page 2- 37...
  • Page 60 VM162/VM172 Chapter 2 Functional Description This page has been intentionally left blank Page 2- 38 © PEP Modular Computers Juli 23, 1997...

  • Page 61: Configuration

    3.3.3 CPU (Bus) Clock...................3-8 3.3.4 SRAM Size .....................3-8 3.3.5 Communications Clock .................3-9 3.3.6 EEPROM Write Protection ................3-9 3.3.7 JTAG Chain....................3-9 3.3.8 SRAM Data Retention .................3-10 3.3.9 BERR1 Timeout...................3-10 3.3.10 Backup Current Test Bridge..............3-10 Juli 23, 1997 © PEP Modular Computers Page 3- 1...
  • Page 62 VM162/VM172 Chapter 3 Configuration Page 3- 2 © PEP Modular Computers Juli 23, 1997...

  • Page 63: Default Jumper Settings

    3.1 Default Jumper Settings The VM162/VM172 has four wire jumpers which can be configured by the user. Additionally, the VM162/VM172 has a set of solder jumpers which are factory set. The list of default settings are shown below. 3.1.1 Jumper Default Settings (Component Side)

  • Page 64: Jumper Description (Component Side)

    VM162/VM172 Chapter 3 Configuration 3.2 Jumper Description (Component Side) Figure 3.1 VM162/VM172 Jumper Layout (Component Side) J1 VME Boot J2 ROM Boot Protective GND VME SYSRES * J10 Signal GND J11 CXC Mode Page 3- 4 © PEP Modular Computers...

  • Page 65: Vme Boot

    Protective ground disconnected from signal ground Default 3.2.4 VME SYSRES* As long as the 5V supply is not within the VMEbus specification, the VM162/VM172 uses the VMEbus RESET line. This behaviour may not be wanted in multi-master configurations and can be disconnected. Jumper...

  • Page 66: Cxc Mode

    16MByte. This is used today in conjunction with the CXM-PFB12 PROFIBUS board. Please consult the relevant CXM User’s Manual to set the CXC mode. Jumper Setting Description Enhanced CXC mode enabled Open Enhanced CXC mode disabled Default Page 3- 6 © PEP Modular Computers Juli 23, 1997...

  • Page 67: Jumper Description (Solder Side)

    Chapter 3 Configuration VM162/VM172 3.3 Jumper Description (Solder Side) Figure 3.2 VM162/VM172 Jumper Layout (Solder Side) Juli 23, 1997 © PEP Modular Computers Page 3- 7...

  • Page 68: Cpu Type

    CPU Bus clock is 25.0 MHz Open CPU Bus clock is 33.3 MHz 3.3.4 SRAM Size Jumper Setting Description J19 - J20 SRAM size is 1 MByte SRAM size is 256 kByte Page 3- 8 © PEP Modular Computers Juli 23, 1997...

  • Page 69: Communications Clock

    Default Open 24 MHz disconnected from 68EN360 RCLK2 pin 3.3.6 EEPROM Write Protection The serial EEPROM stores important data, such as the PEP assigned Ethernet address. In order to pre- vent overwriting, users may set the protection. Jumper Setting Description...

  • Page 70: Sram Data Retention

    Chapter 3 Configuration 3.3.8 SRAM Data Retention The battery backup of the VM162/VM172 is connected to both the SRAM and RTC. This jumper gives the user the possibility to disconnect the SRAM from the battery backup, giving the RTC longer backup support.

  • Page 71: Programming

    Chapter 4 Programming VM162/VM172 Programming 4.1 VM162/VM172 Address Map ............4-3 4.2 Initializing the 68EN360 ............... 4-4 4.3 Initializing the Cache ..............4-7 July 19,1997 © PEP Modular Computers Page 4- 1...
  • Page 72 VM162/VM172 Chapter 4 Programming Page 4- 2 © PEP Modular Computers July 19, 1997...

  • Page 73: Vm162/Vm172 Address Map

    Chapter 4 Programming VM162/VM172 4.1 VM162/VM172 Address Map Address range less than HEX 80 00 00 00 is to be initialized as cachable address areas and address range greater than HEX 80 00 00 00 is to be initialized as non-cachable serialized address area.

  • Page 74: Initializing The 68En360

    6) Lock access to clock divider control register 0x8000.W -> CDVCR 7) Configure CLK lines • COM2 to full strength • COM1 disabled • register access locked 0x83.B -> CLKOCR Page 4- 4 © PEP Modular Computers July 19, 1997...
  • Page 75 0x1F000006.L -> OR3 • CS3: AutoBahn to 0x9000000 0x9000001.L -> BR3 • CS4: size to 16 MByte, port size external, tcyc 1 0x1F000006.L -> OR4 • CS4: SRAM to 0xA000000 0xA000001.L -> BR4 July 19,1997 © PEP Modular Computers Page 4- 5...
  • Page 76 15)If the card is in the first slot, enable the VMEbus monitor If bit 4 in VCSR is set then set bit 5 in VCSR 16)Enable on-board I/O bus error timer Set bit 2 in BCSR Page 4- 6 © PEP Modular Computers July 19, 1997...

  • Page 77: Initializing The Cache

    The easiest way of doing this is to make use of the DTT0 register, in the following way: move.l #$807FE040,d1 movec d1,dtt0 The code above sets all addresses below $80000000 to cacheable and non-serialized, whereas all addresses above are set to non-cacheable and serialized. July 19,1997 © PEP Modular Computers Page 4- 7...
  • Page 78 Accesses to the DRAM and FLASH should be made at $0 and $4000000. All other components addres- sed by the MC68EN360 should always be accessed over the mirrored area with $Cxxxxxxx, as descri- bed in the Address Map Section. Page 4- 8 © PEP Modular Computers July 19, 1997...
  • Page 79 Appendix Memory Piggybacks APPENDIX MEMORY PIGGYBACKS A number of piggybacks have been developed for PEP’s range of CPU boards to enhance their memory capabilities. • DM600 piggyback with 4 MByte DRAM and 1 or 4 MByte FLASH; • DM601piggyback with 16 MByte DRAM and 1 or 4 MByte FLASH;...
  • Page 80 512 kB upper 2 MB Default address range ($4008000- ($4020000- $40100000) $40400000) Flash bank 0 write protected lower 512 kB lower 2 MB Default address range ($4000000- ($4000000- $40080000) $40200000) © PEP Modular Computers Page MEM- 2 July 19, 1997...
  • Page 81 512 kB upper 2 MB Default address range ($4008000- ($4020000- $40100000) $40400000) Flash bank 0 write protected lower 512 kB lower 2 MB Default address range ($4000000- ($4000000- $40080000) $40200000) July 19, 1997 © PEP Modular Computers Page MEM- 3...
  • Page 82 Jumper J2: Flash Bank 0 Write Protection 1 MB FLASH Setting Descirption (29F010) No Protection Default Open Flash bank 0 write protected lower 512 kB Default address range ($4000000- $40080000) © PEP Modular Computers Page MEM- 4 July 19, 1997...
  • Page 83 The DM603 is a memory piggyback fitted with 32MByte DRAM and either 0.5MByte or 2MByte Flash EPROM. Jumper Location DRAM Jumper J1: Flash Write Protection Setting Descirption Open All Flash EPROM write protected No Protection Default July 19, 1997 © PEP Modular Computers Page MEM- 5...
  • Page 84 2 MB Default address range ($4008000- ($4020000- $40100000) $40400000) J2 open Flash bank 0 write protected lower 512 kB lower 2 MB Default address range ($4000000- ($4000000- $40080000) $40200000) July 19, 1997 © PEP Modular Computers Page MEM- 6...
  • Page 85 Appendix SI6 Piggybacks APPENDIX SI6 PIGGYBACKS A number of piggybacks have been developed for PEP’s range of 6U CPU boards to adapt the multi-protocol serial channels of the 68EN360 controller chip to one of the following physical interfaces: • Ethernet 10Base2 (Thin) with SI6-10B2 piggyback;...
  • Page 86 The SI6-10B2 is a physical Cheapernet (10Base2) interface to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards to a 50Ω coax cable via an RG58 BNC ‘T’ connector. The SI6-10B2 has two LEDs fitted; a red LED indicates collision detection and a yellow LED for data.
  • Page 87 + 12 Volts Voltage Common Not connected Not connected Not connected SI6-10B5 required an external +12V from the base board. For more detail, please refer to the relevant Note: base board manual. Juli 23, 1997 © PEP Modular Computers Page SI6- 3...
  • Page 88 The SI6-10BT is a physical twisted pair (10BaseT) interface to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards to an unshielded 100Ω twisted pair cable via an RJ45 telephone jack. The SI6-10BT has two LEDs fitted; a red LED indicates collision detection and a yellow LED for data.
  • Page 89 4.5dB reduced threshold Jumper J2: Link Test Setting Descirption Open Link Test enables Default Link Test disabled Jumper J3: Shielding Setting Descirption Unshielded, 100 Ω termination Open Default Shielded, 150Ω termination Juli 23, 1997 © PEP Modular Computers Page SI6- 5...
  • Page 90 Description SHIELD Shield, Protective Ground resp. Reserved for power RxD+/TxD+ Receive/Transmit Data + CNTR+ Control + DGND Data Ground Voltage Plus Reserver for power RxD-/TxD- Receive/Transmit - CNTR- Control - Page SI6- 6 © PEP Modular Computers Juli 23, 1997...
  • Page 91 Internal idle status Jumper J5:Isolating Voltage Supply Setting Descirption Isolating VCC supplied internally Default Isolating VCC supplied externally Jumper J6: Received Control Setting Descirption Receive permanently enabled Default Receive enabled Juli 23, 1997 © PEP Modular Computers Page SI6- 7...
  • Page 92 Appendix SI6 Piggybacks This page has been intentionally left blank. Page SI6- 8 © PEP Modular Computers Juli 23, 1997...
  • Page 93 When programming FLASH memory, *NEVER* press the RESET button or cyole power! This may da- mage the Bootstrap Loader and will consequently leave the board unusable due to damaged FLASH contents. The ABORT button may be used to cancel a running operation. Juli 23, 1997 © PEP Modular Computers Page BOOT- 1...
  • Page 94 CTRL-x deletes the complete input line while CTRL-a restores the last input line. The start key is a special combination of data appended at the end of the load program. Page BOOT- 2 © PEP Modular Computers Juli 23, 1997...
  • Page 95 (e.g. OS-9: use the 'nopause attribute). Serial parameters can be modified with the pf command. Juli 23, 1997 © PEP Modular Computers Page BOOT- 3...
  • Page 96 In both examples, the programming can be monitored over the term port. The characters displayed have the following meaning: • r Read S-record; valid and in range • t Protected sector touched • e Erase sector • c Copy to buffer, program later • p Program record Page BOOT- 4 © PEP Modular Computers Juli 23, 1997...
  • Page 97 Again, '-c' can be used to clear untouched sectors. Background operation is not supported and it is also not possible to specify an offset. The programming cannot be aborted with ABORT. Juli 23, 1997 © PEP Modular Computers Page BOOT- 5...
  • Page 98 CRC to avoid undesired side effects. In this case, the default of 5 seconds is always used. To validate an invalid CRC, the appropriate utility from an operating system must be used (e.g. ee_config from OS-9). Page BOOT- 6 © PEP Modular Computers Juli 23, 1997...
  • Page 99 '-q' suppress all messages except error messages. '-c' clears all untouched sectors and leaves no old code fragments. For a Load Flash from an absolute address, the -m / -I options must be used. Juli 23, 1997 © PEP Modular Computers Page BOOT- 7...
  • Page 100 Examples Setting term to 300 Baud, 7 Bits/char, odd parity and 2 stopbits: pf term 300/7/o/n Set the bits / character field to 7 for ser0 only: pf ser0 /7 Page BOOT- 8 © PEP Modular Computers Juli 23, 1997...
  • Page 101 Set the stopbits field to 2 for ser0: pf ser0 ///2 Reset System Syntax Description This command exits the Bootstrap Loader and resets the system. It terminates the Bootstrap Loader command mode and resets the complete system, generating a system reset with the on-board watchdog. Help Syntax ? or help...
  • Page 102 Appendix Bootstrap Loader This page has been intentionally left blank. Page BOOT- 10 © PEP Modular Computers Juli 23, 1997...
  • Page 103 The Controller eXtension Connector (CXC) is the local interface. It contains a 16-bit data bus, 7 address lines and 8 deco- ded chip select lines. Each select line has 256 bytes. In total, there are 8 select signals. CXC Address Range Juli 23, 1997 © PEP Modular Computers Page CXC- 1...
  • Page 104 SER2_DTR user defined SER2_CD SER3_DTR SER2_RTS SER1_DTR SER1_CTS SER2_CTS SER1_CD _CS-CXC SER2_TCLK SER3_CTS SER2_RCLK R/_W _SYSR SER2_TXD _UDS SER2_RXD _LDS _EDTACK CXC-CLK _CS2 _CS3 _CS0 _CS4 _CS1 _CS5 _CS6 _CS7 Page CXC- 2 © PEP Modular Computers Juli 23, 1997...
  • Page 105 TXD3 PA7/TXD4/L1RXDA SER3_TXD RXD3 PA6/RXD4/L1TXDA SER3_RXD BRG2 PB7/SMRXD1/_DONE2 user defined PC9/_CD3/_L1RSYNCB SER2_CD RTS2 PB14/_RTS3/_L1RQB/L1ST3 SER2_RTS CTS2 PC8/_CTS3/_L1TSYNCB/SDACK2 SER2_CTS TCLK2 PA12/CLK5/BRGO3/TIN3 SER2_TCLK RCLK2 PA13/CLK6/_TOUT3/L1RCLKB/BRGCLK2 SER2_RCLK TXD2 PA5/TXD3/L1RXDB SER2_TXD RXD2 PA4/RXD3/L1TXDB SER2_RXD Juli 23, 1997 © PEP Modular Computers Page CXC- 3...
  • Page 106 _CXC-CS0 to _CXC-CS7 Recommended: Assert _EDTACK with CSx and _UDS/_LDS and “data valid“ during read cycles Latch data with CSx and _UDS/_LDS during write cycles Negate _EDTACK with _UDS/_LDS invalid Page CXC- 4 © PEP Modular Computers Juli 23, 1997...
  • Page 107 Appendix CXC Controller eXtension Connector Controller Extension Connectors When using an 8TE board on the CXC5 and CXC8 note that a slot will be lost between each board. Juli 23, 1997 © PEP Modular Computers Page CXC- 5...
  • Page 108 Appendix CXC Controller eXtension Connector This page has been intentionally left blank Page CXC- 6 © PEP Modular Computers Juli 23, 1997...
  • Page 109 This Appendix outlines the connection definitions of =S-9 systems to various outside media. OS-9 System <-> Terminal Software (XON/XOFF) or no Handshake 1.1.1 15-pin Connector on OS-9 Side 1.1.2 8-pin RJ45 Connector on OS-9 Side (SMART I/O) November 21, 1996 © PEP Modular Computers Page OS- 1...
  • Page 110 Appendix OS-9 Cabling 1.1.3 6-pin RJ12 Connector on OS-9 Side Page OS- 2 © PEP Modular Computers Novemeber 21, 1996...
  • Page 111 Appendix OS-9 Cabling Hardware Handshake (Set Terminal to CTS/DTR Handshake) 1.2.1 15-pin Connector on OS-9 Side 1.2.2 8-pin RJ45 Connector on OS-9 Side (SMART I/O) November 21, 1996 © PEP Modular Computers Page OS- 3...
  • Page 112 OS-9 System <-> PC Software (XON/XOFF) or no Handshake 2.1.1 15-pin Connector on OS-9 Side, 25-pin Connector on PC Side 2.1.2 15-pin Connector on OS-9 Side, 9-pin Connector on PC Side Page OS- 4 © PEP Modular Computers Novemeber 21, 1996...
  • Page 113 Appendix OS-9 Cabling 2.1.3 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 25-pin Connector on PC Side 2.1.4 6-pin RJ12 Connector on OS-9 Side, 25-pin Connector on PC Side November 21, 1996 © PEP Modular Computers Page OS- 5...
  • Page 114 Appendix OS-9 Cabling 2.1.5 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 9-pin Connector on PC Side 2.1.6 6-pin RJ12 Connector on OS-9 Side, 9-pin Connector on PC Side Page OS- 6 © PEP Modular Computers Novemeber 21, 1996...
  • Page 115 Hardware Handshake (Select RTS/CTS Handshake on the PC Side) 2.2.1 15-pin Connector on OS-9 Side, 25-pin Connector on PC Side 2.2.2 15-pin Connector on OS-9 Side, 9-pin Connector on PC Side...
  • Page 116 Appendix OS-9 Cabling 2.2.3 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 25-pin Connector on PC Side 2.2.4 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 9-pin Connector on PC Side Page OS- 8 © PEP Modular Computers Novemeber 21, 1996...
  • Page 117 OS-9 System <-> Modem 15-pin Connector 8-pin RJ45 Connector (SMART I/O)
  • Page 118 Appendix OS-9 Cabling OS-9 System <-> OS-9 System Software (XON/XOFF) or no Handshake 4.1.1 15-pin Connector 4.1.2 8-pin RJ45 Connector (SMART I/O) 4.1.3 6-pin RJ12 Connector Page OS- 10 © PEP Modular Computers Novemeber 21, 1996...
  • Page 119 Hardware Handshake 4.2.1 15-pin Connector 4.2.2 8-pin RJ45 Connector (SMART I/O)
  • Page 120 Appendix OS-9 Cabling This page has been intentionally left blank Page OS- 12 © PEP Modular Computers Novemeber 21, 1996...

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