Mitsubishi Electric MELSEC Q Series Handbook page 203

7
REPLACEMENT OF PROGRAM
Left rotation of 32-bit data
Right rotation of 32-bit data
1-word shift to left of n-word data
1-word shift to right of n-word data
32 bit data checks
2-word data write to the intelligent/special function
module
Timing pulse generation
32-bit data conversion
32-bit data non-exclusive logical sum operations
32-bit exclusive logical sum operations
Interrupt enable instruction
Link refresh enable
256  8-bit encode
Sequence program termination
Main routine program termination
Reading oldest data from tables
Writing data to the data table
Identical 16-bit data block transfers
FOR to NEXT instruction
1-word data read from the intelligent/
special function module
16-bit BIN data increment
Return from interrupt programs
Pointer branch instruction
Operation start
BIN 16-bit data comparison
BIN 32-bit data comparison
Operation start
ASCII code display instruction
*1 Note that the buffer memory address between Q series and AnS series may differ.
Description
AnSCPU QnUCPU
Instruction name Instruction name Conversion
DROL DROL
DROLP DROLP
DROR DROR
DRORP DRORP
DSFL DSFL
DSFLP DSFLP
DSFR DSFR
DSFRP DSFRP
DSUM DSUM
DSUMP DSUMP
DTO DTO
DTOP DTOP
DUTY DUTY
DXCH DXCH
DXCHP DXCHP
DXNR DXNR
DXNRP DXNRP
DXOR DXOR
DXORP DXORP
EI EI
EI EI
ENCO ENCO
ENCOP ENCOP
END END
FEND FEND
FIFR FIFR
FIFRP FIFRP
FIFW FIFW
FIFWP FIFWP
FMOV FMOV
FMOVP FMOVP
FOR FOR
FROM FROM
FROMP FROMP
INC INC
INCP INCP
IRET IRET
JMP JMP
LD LD
LD< LD<
LD<= LD<=
LD<> LD<>
LD= LD=
LD> LD>
LD>= LD>=
LDD< LDD<
LDD<= LDD<=
LDD<> LDD<>
LDD= LDD=
LDD> LDD>
LDD>= LDD>=
LDI LDI
LED OUT SM1255
Reference
 Section 7.7.8
 Section 7.7.8
 Section 7.7.8
 Section 7.7.8
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Section 7.7.8
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 Section 7.7.8
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Section 7.2.3 (3)
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