Register Structure - Advantech MIC-3612/3-BE User Manual

4.1

Register Structure

This chapter gives short descriptions of each of the module's registers. For more
information please refer to the data book for the OX16C850 UART chip.
All registers are one byte. Bit 0 is the least significant bit, and bit 7 is the most signifi-
cant bit. The address of each register is specified as an offset from the port base
address (BASE).
BASE+1 Interrupt Enable Register (IER)
Bit0 Enable received-data-available interrupt
Bit1 Enable transmitter-holding-register-empty interrupt
Bit2 Enable receiver-line-status interrupt
Bit3 Enable modem-status interrupt
Bit4: Sleep Mode Enable (requires EFR bit-4 = 1)
Bit5: Xoff Interrupt Enable (requires EFR bit-4=1)
Bit6: RTS# Output Interrupt Enable (requires EFR bit-4=1)
Bit7: CTS# Input Interrupt Enable (requires EFR bit-4=1)
BASE+2 (read) Interrupt status register (ISR)
Table 4.1: BASE+2 (read) Interrupt status register (ISR)
Register
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Table 4.2: Interrupt Source And Priority Level
Level ISR[5:0]
1 000110
2 001100
3 000100
4 000010
5 000000
6 010000
7 100000
- 000001
MIC-3612/3-BE User Manual
ISR
Interrupt pending
Interrupt priority
FIFO Enable Status
Interrupt source
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Receive Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default)
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