Status - Quectel UG89 Hardware Design

I2C_SDA 28
Clock and mode can be configured by AT command, and the default configuration is short frame
synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC.
The following figure shows a reference design of a PCM interface with external codec IC.
Module
Figure 19: Reference Circuit of PCM Application with Audio Codec
NOTE
It is recommended to reserve an RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.

3.12. STATUS

The STATUS pin is an open drain output for the module's operation status indication. It can be connected
to a GPIO of DTE with a pulled-up resistor, or as an LED indication circuit as below. When the module is
turned on normally, the STATUS will present the low state. Otherwise, the STATUS will present high-
impedance state.
Table 19: Pin Definition of STATUS
UG89_Hardware_Design
external codec
I2C serial data for an external
OD
codec
PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
I2C_SCL
I2C_SDA
1.8V
UMTS/HSPA+ Module Series
is required.
If unused, it is recommended to
mount a 33pF capacitor close to
the pin.
An external 1.8V pull-up resistor
is required.
If unused, keep it open.
MICBIAS
INP
BCLK
INN
LRCK
DAC
ADC
LOUTP
SCL
SDA
LOUTN
Codec
UG89 Hardware Design
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