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UART1_CTS
11
UART1_RTS
14
UART1_DTR
46
UART1_TXD
10
UART1_RXD
12
UART1_DSR
44
Table 12: Pin Definition of the Debug UART Interface
Pin Name
Pin No.
DBG_RXD
30
DBG_TXD
31
DBG_RTS
32
DBG_CTS
33
The logic levels are described in the following table.
Table 13: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
The module provides a 1.8V UART interface. A level translator should be used if the application is equipped
with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is
recommended. The following figure shows a reference design.
UG89_Hardware_Design
DO
DTE clear to send
DI
DTE request to send
DI
Data terminal ready
DO
Transmit data
DI
Receive data
DO
Data set ready
I/O
Description
DI
Debug receive data
DO
Debug transmit data
DI
Debug request to send
DO
Debug clear to send
Min.
-0.3
1.2
0
1.35
UMTS/HSPA+ Module Series
UG89 Hardware Design
Comment
1.8V power domain.
Max.
0.6
2.0
0.45
1.8
Unit
V
V
V
V
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