Glossary - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs

Glossary

7 Glossary
Table 36 Glossary
Terms
AUDIOSS
CAN FD
CLK_FAST_0
CLK_FAST_1
CLK_GR
CLK_HF
CLK_MEM
CLK_PERI
CLK_SLOW
Clock Calibration Counter
CSV
CXPI
ECO
EXT_CLK
FLL
FPU
ILO
IMO
LIN
LPECO
Peripheral clock divider
PLL#0
PLL#1
PLL#2
PLL#3
SAR ADC
Application Note
Audio subsystem. See the "Audio subsystem" chapter of TRAVEO™ T2G
architecture TRM for details.
CAN FD is the CAN with flexible data rate, and CAN is the controller area
network. See the "CAN FD controller" chapter of TRAVEO™ T2G
TRM for details.
Fast clock. The CLK_FAST is used for the CM7 and CPUSS fast infrastructure.
Fast clock. The CLK_FAST is used for the CM7 and CPUSS fast infrastructure.
Group clock. The CLK_GR is the clock input to peripheral functions.
High-frequency clock. The CLK_HF derives both CLK_FAST and CLK_SLOW.
CLK_HF, CLK_FAST, and CLK_SLOW are synchronous to each other.
Memory clock. The CLK_MEM clocks the CPUSS fast infrastructure.
Peripheral clock. The CLK_PERI is the clock source for CLK_SLOW, CLK_GR and
peripheral clock divider.
Slow clock. The CLK_FAST is used for the CM0+ and CPUSS slow infrastructure.
Clock calibration counter has a function to calibrate the clock using two
clocks.
Clock supervision
Clock extension peripheral interface. See the "Clock extension peripheral
interface (CXPI)" chapter of the TRAVEO™ T2G
External crystal oscillator
External clock
Frequency-locked loop
Floating point unit
Internal low-speed oscillators
Internal main oscillator
Local interconnect network. See the "Local interconnect network (LIN)"
chapter of the TRAVEO™ T2G
Low-power external crystal oscillator
The peripheral clock divider derives a clock for use in each peripheral function.
Phase-locked loop. This PLL is not implemented with SSCG and fractional
operation.
Phase-locked loop. This PLL is not implemented with SSCG and fractional
operation.
Phase-locked loop. This PLL is implemented with SSCG and fractional
operation.
Phase-locked loop. This PLL is implemented with SSCG and fractional
operation.
Successive approximation register analog-to-digital converter. See the "SAR
ADC" chapter of the TRAVEO™ T2G
75 of 80
Description
architecture TRM
architecture TRM for details.
architecture TRM
architecture
for details.
for details.
002-26071 Rev. *B
2021-09-07