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Infineon TRAVEO T2G family CYT4D Series Manual

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AN226071
Clock configuration setup in TRAVEO™ T2G
family CYT4D series MCUs
About this document
Scope and purpose
AN226071 describes how to set up the various clock sources in TRAVEO™ T2G family CYT4D series MCUs and
provides examples including configuring PLL/FLL and calibrating the ILO.
Associated part family
TRAVEO™ T2G family CYT4D series automotive microcontrollers
Intended audience
This document is intended for users who use the clock configuration setup in TRAVEO™ T2G family CYT4D series
MCUs.
Table of contents
About this document ......................................................................................................................... 1
Table of contents .............................................................................................................................. 1
1
Introduction ............................................................................................................................ 3
2
Clock system for TRAVEO™ T2G family MCUs ............................................................................... 4
2.1
Overview of the clock system ................................................................................................................. 4
2.2
Clock resources ....................................................................................................................................... 4
2.3
Clock system functions ........................................................................................................................... 4
2.4
Basic clock system settings ................................................................................................................... 11
3
Configuration of the clock resources .........................................................................................12
3.1
Setting the ECO ..................................................................................................................................... 12
3.1.1
Use case ............................................................................................................................................ 13
3.1.2
Configuration ................................................................................................................................... 13
3.1.3
Sample code for initial ECO configuration ...................................................................................... 14
3.2
Setting WCO ........................................................................................................................................... 20
3.2.1
Operation overview .......................................................................................................................... 20
3.2.2
Configuration ................................................................................................................................... 20
3.2.3
Sample code for the initial configuration of WCO settings ............................................................ 21
3.3
Configuring IMO ..................................................................................................................................... 22
3.4
Configuring ILO0/ILO1 ........................................................................................................................... 22
3.5
Setting the LPECO ................................................................................................................................. 23
3.5.1
Use case ............................................................................................................................................ 23
3.5.2
Sample code for the initial configuration of LPECO settings ......................................................... 24
4
Configuration of the FLL and PLL ..............................................................................................26
4.1
Setting FLL ............................................................................................................................................. 26
4.1.1
Operation overview .......................................................................................................................... 26
Application Note
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 80
002-26071 Rev. *B
2021-09-07

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Summary of Contents for Infineon TRAVEO T2G family CYT4D Series

  • Page 1 Configuration of the FLL and PLL ....................26 Setting FLL ............................. 26 4.1.1 Operation overview .......................... 26 Application Note Please read the Important Notice and Warnings at the end of this document 002-26071 Rev. *B www.infineon.com page 1 of 80 2021-09-07...

  • Page 2: Table Of Contents

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Table of contents 4.1.2 Use case ............................27 4.1.3 Configuration ........................... 27 4.1.4 Sample code for the initial configuration of FLL settings ............... 28 Setting PLL ............................. 31 4.2.1 Use case ............................33 4.2.2 Configuration ...........................
  • Page 3 (HUD), have a 2D graphics engine, sound processing, 32-bit automotive microcontrollers based on the Arm® Cortex®-M7 processor with FPU (single and dual precision), and manufactured on an advanced 40-nm process technology. These products enable a secure computing platform, and incorporate Infineon low-power flash memory along with multiple high-performance analog and digital functions.
  • Page 4 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Clock system for TRAVEO™ T2G family MCUs Clock system for TRAVEO™ T2G family MCUs Overview of the clock system The clock system in this series of MCUs is divided into two blocks. One block selects the clock resources (such as external oscillation and internal oscillation) and multiplies the clock (using FLL and PLL).
  • Page 5 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Clock system for TRAVEO™ T2G family MCUs supported clock resources, FLL, and PLL to generate the required high-speed clocks. These MCUs support two types of PLLs: PLL without spread spectrum clock generation (SSCG) and fractional operation (PLL200#x), and PLL with SSCG and fractional operation (PLL400#x).
  • Page 6 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Clock system for TRAVEO™ T2G family MCUs Active domain Region of operation in only Active power mode DeepSleep domain Region of operation in only Active and DeepSleep modes Hibernate domain Region of operation in all power modes ECO prescaler Divides the ECO and creates a clock that can be used with the CLK_LF clock.
  • Page 7 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Clock system for TRAVEO™ T2G family MCUs Figure 3 shows the distribution of the CLK_HF0. The CLK_HF0 is the root clock for the CPU subsystem (CPUSS) and peripheral clock dividers. For details on Figure 3, see the architecture TRM...
  • Page 8 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Clock system for TRAVEO™ T2G family MCUs CLK_TRC_DBG Clock input to the CPUSS (DEBUG). Divider Divider has a function to divide each clock. It can be configured from 1 division to 256 divisions.
  • Page 9 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Clock system for TRAVEO™ T2G family MCUs Figure 5 shows the distribution of the CLK_HF1. The CLK_HF1 is a clock source of the CLK_FAST_0 and CLK_FAST_1. The clock distribution of the CLK_HF1 is shown in Figure 5.
  • Page 10 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Clock system for TRAVEO™ T2G family MCUs Figure 7 shows details of the peripheral clock divider #1. The peripheral clock divider #1 has many peripheral clock dividers to generate the PCLK. See the datasheet the number of dividers.
  • Page 11 Basic clock system settings This section describes how to configure the clock system based on a use case using the sample driver library (SDL) provided by Infineon. The code snippets in this application note are part of the SDL. See Other references.
  • Page 12 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Configuration of the clock resources Setting the ECO The ECO is disabled by default and needs to be enabled for usage. Also, trimming is necessary to use the ECO. This device can configured with the trimming parameters that control the oscillator according to crystal unit and ceramic resonator.
  • Page 13 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources 3.1.1 Use case Oscillator to use: Crystal unit • Fundamental frequency: 16 MHz • Maximum drive level: 300.0 µW • Equivalent series resistance: 150.0 ohm •...
  • Page 14 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Parameters Description Value ESR_IN_OHM Equivalent series resistance (ESR) (ohm) 250ul MAX_DRIVE_LEVEL_IN_UW Maximum drive level (uW) 100ul MIN_NEG_RESISTANCE Minimum negative resistance 5 * ESR_IN_OHM Table 2 List of ECO trim settings functions Functions Description...
  • Page 15 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Code Listing 1 General configuration of ECO settings /** Wait time definition **/ Define the TIMEOUT variable. #define WAIT_FOR_STABILIZATION (10000ul) #define CLK_FREQ_ECO (16000000ul) Define the oscillator parameters to use for software calculation. #define PLL_400M_0_PATH_NO (1ul) #define PLL_400M_1_PATH_NO...
  • Page 16 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Code Listing 3 Cy_SysClk_EcoEnable() function cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) cy_en_sysclk_status_t rtnval; /* invalid state error if ECO is already enabled */ (2) Check if ECO_OK is already enabled. if (SRSS->unCLK_ECO_CONFIG.stcField.u1ECO_EN != 0ul) /* 1 = enabled */ (3) Write “1”...
  • Page 17 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Code Listing 4 Cy_SysClk_EcoConfigureWithMinRneg() function gtrim = Cy_SysClk_SelectEcoGtrim(gm_min); if(gtrim == CY_SYSCLK_INVALID_TRIM_VALUE) Get the Gtrim value. See Code Listing return(CY_SYSCLK_BAD_PARAM); Get then Rtrim value. See Code Listing rtrim = Cy_SysClk_SelectEcoRtrim(freqMHz);...
  • Page 18 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Code Listing 5 Cy_SysClk_SelectEcoAtrim () function return(0x00ul); else // invalid input return(CY_SYSCLK_INVALID_TRIM_VALUE); Code Listing 6 Cy_SysClk_SelectEcoAGCEN() function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoAGCEN(float32_t maxAmplitude) if((0.50f <= maxAmplitude) && (maxAmplitude < 1.10f)) Get the AGC enable setting.
  • Page 19 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Code Listing 8 Cy_SysClk_SelectEcoGtrim() function else if(gm_min < 6.6f) return(0x02ul+1ul); else if(gm_min < 8.8f) return(0x03ul+1ul); else if(gm_min < 11.0f) return(0x04ul+1ul); else if(gm_min < 13.2f) return(0x05ul+1ul); else if(gm_min <...
  • Page 20 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Setting WCO 3.2.1 Operation overview The WCO is disabled by default. Accordingly, the WCO cannot be used unless it is enabled. Figure 10 shows how to configure registers for enabling the WCO.
  • Page 21 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Functions Description Value Cy_SysClk_FllDisable Disable FLL Wait Cycle = Sequence(Wait Cycle) WAIT_FOR_STABILIZATION Cy_SysClk_Pll400M Disable PLL400M_0 PLL number = Disable(PLL Number) PLL_400M_0_PATH_NO Disable PLL400M_1 PLL number = PLL_400M_1_PATH_NO Cy_SysClk_PllDisable Disable the PLL200M_0...
  • Page 22 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Code Listing 12 AllClockConfiguration () function static void AllClockConfiguration(void) /***** WCO setting ******/ cy_en_sysclk_status_t wcoStatus; WCO enable. See Code Listing wcoStatus = Cy_SysClk_WcoEnable(WAIT_FOR_STABILIZATION*10ul); CY_ASSERT(wcoStatus == CY_SYSCLK_SUCCESS); return;...
  • Page 23 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Setting the LPECO The LPCEO is disabled by default. The LPECO cannot be used unless it is enabled. Figure 11 shows how to configure registers for enabling the LPECO. To disable the LPECO, write ‘0’ to the LPECO_EN bit of the BACKUP_LPECO_CTL register.
  • Page 24 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Table 6 List of LPECO settings functions Functions Description Value Cy_WDT_Disable() Disable the watchdog timer. – Set the load capacitance range for the CY_SYSCLK_BAK_LPECO_LC Cy_SysClk_ClkBak_LPECO_Se tLoadCap(range) LPECO crystal.
  • Page 25 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the clock resources Code Listing 15 AllClockConfiguration () function static void AllClockConfiguration(void) #ifdef LPECO_ENABLE /***** LPECO setting ******/ (1) Configure the value to Cy_SysClk_ClkBak_LPECO_SetLoadCap(CY_SYSCLK_BAK_LPECO_LCAP_5TO10PF); BACKUP_LPECO_CTL. See Code Listing Cy_SysClk_ClkBak_LPECO_SetFrequency(CY_SYSCLK_BAK_LPECO_FREQ_6TO8MHZ);...
  • Page 26 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Configuration of the FLL and PLL This section describes the configuring of the FLL and PLL in the clock system. Setting FLL 4.1.1 Operation overview The FLL must be set before using it.

  • Page 27: Use Case

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL 4.1.2 Use case Input clock frequency: 16 MHz • Output clock frequency: 100 MHz • 4.1.3 Configuration Table 7 lists the parameters and Table 8 lists the functions of the configuration part of in the SDL for FLL settings.

  • Page 28: Sample Code For The Initial Configuration Of Fll Settings

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL 4.1.4 Sample code for the initial configuration of FLL settings Code Listing 21 Code Listing 25 show the sample code. Code Listing 21 General configuration of FLL settings /** Wait time definition **/ Define the TIMEOUT variable.
  • Page 29 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 23 Cy_SysClk_FllConfigureStandard() function SRSS->unCLK_FLL_CONFIG3.stcField.u2BYPASS_SEL = (uint32_t)outputMode; return(CY_SYSCLK_SUCCESS); FLL parameter calculation cy_stc_fll_manual_config_t config = { 0ul }; config.outputMode = outputMode; /* 1. Output division is not required for standard accuracy. */ config.enableOutputDiv = false;...
  • Page 30 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 24 Cy_SysClk_FllManualConfigure() function cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config) cy_en_sysclk_status_t returnStatus = CY_SYSCLK_SUCCESS; (1) Check if the FLL is already enabled. /* check for errors */ if (SRSS->unCLK_FLL_CONFIG.stcField.u1FLL_ENABLE != 0ul) /* 1 = enabled */ returnStatus = CY_SYSCLK_INVALID_STATE;...

  • Page 31: Setting Pll

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 25 Cy_SysClk_FllEnable() function cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) /* first set the CCO enable bit */ SRSS->unCLK_FLL_CONFIG4.stcField.u1CCO_ENABLE = 1ul; (3) Enable the CCO. /* Wait until CCO is ready */ (4) Wait until the CCO is available.
  • Page 32 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Case: PLL400 Start PLL400M already enabled? Based on the specification of the application, PLL400M configuration configure PLL400M to each register. Use Fractional Divider ? Fractional divider settings Fractional divider setting Enable fractional divider...

  • Page 33: Use Case

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL 4.2.1 Use case Input clock frequency: 16.000 MHz • Output clock frequency: • 250.000 MHz (PLL400 #0) 196.608 MHz (PLL400 #1) 160.000 MHz (PLL200 #0) 80.000 MHz (PLL200 #1) Fractional divider: •...
  • Page 34 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Parameters Description Value Selects the FLL output. Ignores then lock indicator. See SRSS_CLK_FLL_CONFIG3 in the registers for details. pllConfig.inputFreq Input PLL frequency PATH_SOURCE_CLOCK_ FREQ pllConfig.outputFreq Output PLL frequency (PLL400 #0) PLL400_0_TARGET_FREQ...
  • Page 35 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Parameters Description Value manualConfig.outputMode Bypass mux located just after PLL output: config->outputMode (Calculated value) 0: AUTO 1: LOCKED_OR_NOTHING 2: PLL_REF 3: PLL_OUT Table 10 List of PLL 400 settings functions Functions Description...
  • Page 36 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Functions Description Value Cy_SysClk_Pll400M Set the PLL path number and monitor the PLL number = Enable(PLL Number,Timeout PLL configuration (PLL400 #0). PLL400_0_PATH_NO, value) Timeout value = WAIT_FOR_STABILIZATION Set the PLL path number and monitor the PLL number =...
  • Page 37 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Parameters Description Value manualConfig.lfMode VCO frequency range selection: config->lfMode (Calculated value) 0: VCO frequency is [200 MHz, 400 MHz] 1: VCO frequency is [170 MHz, 200 MHz) manualConfig.outputMode Bypass mux located just after PLL output: config->outputMode...
  • Page 38 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Functions Description Value Cy_SysClk_PllCaluc Calculate the appropriate divider settings InputFreq = Dividers(InputFreq, according to the PLL input/output PATH_SOURCE_CLOCK_ OutputFreq,PLLlimit,FracBi frequency. FREQ tNum,RefDiv,OutputDiv,Feed BackFracDiv) OutputFreq = PLL400_0_TARGET_FREQ (PLL 400 #0), PLL400_1_TARGET_FREQ...

  • Page 39: Sample Code For The Initial Pll Configuration

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL 4.2.3 Sample code for the initial PLL configuration Code Listing 26 Code Listing 32 show the sample code for the PLL400 #0 example; Code Listing 33 Code Listing 39 show the sample code for the PLL200 #0 example.
  • Page 40 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 28 Cy_SysClk_Pll400MConfigure() function cy_en_sysclk_status_t Cy_SysClk_Pll400MConfigure(uint32_t clkPath, const cy_stc_pll_400M_config_t *config) /* check for error */ uint32_t pllNo; Check for valid clock path and PLL400 cy_en_sysclk_status_t status = Cy_SysClk_GetPll400MNo(clkPath, &pllNo);...
  • Page 41 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 29 Cy_SysClk_Pll400MManualConfigure() function if((config->feedbackDiv < PLL_400M_MIN_FB_DIV) || (PLL_400M_MAX_FB_DIV < config->feedbackDiv)) return(CY_SYSCLK_BAD_PARAM); un_CLK_PLL400M_CONFIG_t tempClkPLL400MConfigReg; tempClkPLL400MConfigReg.u32Register = SRSS->CLK_PLL400M[pllNo].unCONFIG.u32Register; if (tempClkPLL400MConfigReg.stcField.u1ENABLE != 0ul) /* 1 = enabled */ return(CY_SYSCLK_INVALID_STATE);...
  • Page 42 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 31 Cy_SysClk_PllCalucDividers() function return (CY_SYSCLK_BAD_PARAM); if(refDiv == NULL) return (CY_SYSCLK_BAD_PARAM); if(outputDiv == NULL) return (CY_SYSCLK_BAD_PARAM); if ((targetOutFreq < lim->minFoutput) || (lim->maxFoutput < targetOutFreq)) return (CY_SYSCLK_BAD_PARAM);...
  • Page 43 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 31 Cy_SysClk_PllCalucDividers() function return (CY_SYSCLK_SUCCESS); Code Listing 32 Cy_SysClk_Pll400MEnable() function cy_en_sysclk_status_t Cy_SysClk_Pll400MEnable(uint32_t clkPath, uint32_t timeoutus) uint32_t pllNo; cy_en_sysclk_status_t status = Cy_SysClk_GetPll400MNo(clkPath, &pllNo); if(status != CY_SYSCLK_SUCCESS) return(status);...
  • Page 44 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 34 AllClockConfiguration() function static void AllClockConfiguration(void) /***** PLL200M#0(PATH3) source setting ******/ PLL200 configuration. See Code Listing 35 status = Cy_SysClk_PllConfigure(PLL_200M_0_PATH_NO , &g_pll200_0_Config); CY_ASSERT(status == CY_SYSCLK_SUCCESS);...
  • Page 45 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 36 Cy_SysClk_PllManualConfigure() function if((config->referenceDiv < MIN_REF_DIV) || (MAX_REF_DIV < config->referenceDiv)) return(CY_SYSCLK_BAD_PARAM); if((config->feedbackDiv < (config->lfMode ? MIN_FB_DIV_LF : MIN_FB_DIV_NORM)) || ((config->lfMode ? MAX_FB_DIV_LF : MAX_FB_DIV_NORM) < config->feedbackDiv)) return(CY_SYSCLK_BAD_PARAM);...
  • Page 46 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 38 Cy_SysClk_PllCalucDividers() function return (CY_SYSCLK_BAD_PARAM); if(outputDiv == NULL) return (CY_SYSCLK_BAD_PARAM); if ((targetOutFreq < lim->minFoutput) || (lim->maxFoutput < targetOutFreq)) return (CY_SYSCLK_BAD_PARAM); /* REFERENCE_DIV selection */ for (uint32_t i_refDiv = lim->minRefDiv;...
  • Page 47 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuration of the FLL and PLL Code Listing 39 Cy_SysClk_PllEnable() function cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) uint32_t pllNo; cy_en_sysclk_status_t status = Cy_SysClk_GetPllNo(clkPath, &pllNo); if(status != CY_SYSCLK_SUCCESS) return(status); /* first set the PLL enable bit */ (10) Enable PLL200 SRSS->unCLK_PLL_CONFIG[pllNo].stcField.u1ENABLE = 1ul;...

  • Page 48: Configuring The Internal Clock

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Configuring the internal clock This section describes how to configure the internal clocks as part of the clock system. Configuring CLK_PATHx The CLK_PATHx is used as the input source for the root clock, CLK_HFx. The CLK_PATHx can select all clock resources including the FLL and PLL using DSI_MUX and PATH_MUX.
  • Page 49 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Table 14 Configuring CLK_PATHx Register name Bit name Value Selected clock and item CLK_PATH_SELECT PATH_MUX[2:0] 0 (Default) IMO EXT_CLK DSI_MUX LPECO other Reserved. Do not use. CLK_DSI_SELECT DSI_MUX[4:0] ILO0...

  • Page 50: Configuring Clk_Hfx

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Configuring CLK_HFx The CLK_HFx (x = 0 to 13) can be selected from CLK_PATHy (y= 0 to 9). A predivider is available to divide the selected CLK_PATHx. The CLK_HF0 is always enabled because it is the source clock for the CPU cores. It is possible to disable CLK_HFx.

  • Page 51: Configuring The Clk_Lf

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Configuring the CLK_LF The CLK_LF can be selected from one of the possible sources WCO, ILO0, ILO1, ECO_Prescaler, and LPECO_Prescaler. The CLK_LF cannot be configured when the WDT_LOCK bit in the WDT_CLTL register is disabled because the CLK_LF can select the ILO0 that is the input clock for the WDT.

  • Page 52: Configuring Clk_Slow

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Configuring CLK_SLOW The CLK_SLOW is generated by dividing the CLK_MEM; its frequency is configured by the value obtained by dividing CLK_MEM by (x+1). After configuring the CLK_MEM, configure a value divided (x= 0 to 255) by the INT_DIV bit of the CPUSS_SLOW_CLOCK_CTL register.

  • Page 53: Configuring Pclk

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Configuring PCLK The PCLK is a clock that activates each peripheral function. Peripheral clock dividers have a function to divide the CLK_PERI and generate a clock to be supplied to each peripheral function. For assignment of the peripheral clocks, see the “Peripheral clocks”...

  • Page 54: Example Of Pclk Setting

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock 5.9.1 Example of PCLK setting 5.9.1.1 Use case Input clock frequency: 80 MHz • Output clock frequency: 2 MHz • Divider type: Clock divider 16.0 • Used divider: Clock divider 16.0#0 •...

  • Page 55: Sample Code For The Initial Configuration Of Pclk Settings (Example Of The Tcpwm Timer)

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Parameters Description Value targetFreq Target clock frequency 2000000ul (2 MHz) divNum Divide number periFreq/targetFreq Table 18 List of PCLK (Example of the TCPWM timer) settings functions Functions Description Value...
  • Page 56 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Code Listing 41 Cy_SysClk_PeriphAssignDivider() function __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum) un_PERI_CLOCK_CTL_t tempCLOCK_CTL_RegValue; tempCLOCK_CTL_RegValue.u32Register = PERI->unCLOCK_CTL[ipBlock].u32Register; (2) Assign the divider to the tempCLOCK_CTL_RegValue.stcField.u2TYPE_SEL = dividerType; peripheral.

  • Page 57: Setting Eco_Prescaler

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock 5.10 Setting ECO_Prescaler The ECO_Prescaler divides the ECO, and creates a clock that can be used with the CLK_LF. The division function has a 10-bit integer divider and 8-bit fractional divider. Figure 19 shows the steps to enable the ECO_Prescaler.

  • Page 58: Use Case

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock 5.10.1 Use case Input clock frequency: 16 MHz • ECO prescaler target frequency: 1.234567 MHz • 5.10.2 Configuration Table 19 lists the parameters and Table 20 lists the functions of the configuration part of in the SDL for ECO prescaler settings.

  • Page 59: Sample Code For The Initial Configuration Of Eco Prescaler Settings

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock 5.10.3 Sample code for the initial configuration of ECO prescaler settings Code Listing 44 Code Listing 50 show the sample code. Code Listing 44 General configuration of ECO prescaler settings #define ECO_PRESCALER_TARGET_FREQ (1234567ul) Define the ECO prescaler target frequency.
  • Page 60 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Code Listing 47 Cy_SysClk_SetEcoPrescaleManual() function __STATIC_INLINE void Cy_SysClk_SetEcoPrescaleManual(uint16_t divInt, uint8_t divFract) (1) Configure the ECO prescaler. un_CLK_ECO_PRESCALE_t tempRegEcoPrescale; tempRegEcoPrescale.u32Register = SRSS->unCLK_ECO_PRESCALE.u32Register; tempRegEcoPrescale.stcField.u10ECO_INT_DIV = divInt; tempRegEcoPrescale.stcField.u8ECO_FRAC_DIV = divFract; SRSS->unCLK_ECO_PRESCALE.u32Register = tempRegEcoPrescale.u32Register;...

  • Page 61: Configuring The Lpeco_Prescaler

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock 5.11 Configuring the LPECO_Prescaler The LPECO_Prescaler divides the LPECO. The division function has a 10-bit integer divider and 8-bit fractional divider. Figure 21 shows the steps to enable the LPECO_Prescaler. For details on the LPECO_Prescaler, see the architecture TRM.

  • Page 62: Configuration

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock 5.11.2 Configuration Table 21 lists the parameters and Table 22 lists the functions of the configuration part of in the SDL for LPECO prescaler settings. Table 21 List of LPECO prescaler settings parameters Parameters Description...
  • Page 63 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Code Listing 52 AllClockConfiguration() function static void AllClockConfiguration(void) /***** LPECO prescaler setting ******/ LPECO prescaler setting. See Code Listing cy_en_sysclk_status_t lpecoPreStatus; lpecoPreStatus = Cy_SysClk_ClkBak_LPECO_SetPrescale(CLK_FREQ_LPECO, LPECO_PRESCALER_TARGET_FREQ); CY_ASSERT(lpecoPreStatus == CY_SYSCLK_SUCCESS); lpecoPreStatus = Cy_SysClk_ClkBak_LPECO_PrescaleEnable(WAIT_FOR_STABILIZATION);...
  • Page 64 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Configuring the internal clock Code Listing 55 Cy_SysClk_ClkBak_LPECO_PrescaleEnable() function return CY_SYSCLK_TIMEOUT; Cy_SysLib_DelayUs(1u); timeoutus--; return CY_SYSCLK_SUCCESS; Code Listing 56 Cy_SysClk_ClkBak_LPECO_PrescalerOkay() function __STATIC_INLINE bool Cy_SysClk_ClkBak_LPECO_PrescalerOkay(void) if(BACKUP->unLPECO_PRESCALE.stcField.u1LPECO_DIV_ENABLED == 1) Check the prescaler status. return true;...

  • Page 65: Supplementary Information

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information Supplementary information Input clocks in peripheral functions Table 23 Table 30 list the clock input to each peripheral function. For detailed values of PCLK, see the “Peripheral clocks” section of the datasheet. Table 23 Clock input to TCPWM[0] Peripheral function...

  • Page 66: Use Case Of The Clock Calibration Counter Function

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information Table 27 Clock input to SAR ADC Peripheral function Operation clock Unit clock SAR ADC CLK_GR9 (Group 9) Unit0: PCLK (PCLK_PASS_CLOCK_SAR0) Table 28 Clock input to CXPI Peripheral function Operation clock Channel clock CXPI...

  • Page 67: Use Case

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information Start Configure ECO and ILO0 Set ECO to Conuter 1 Set ILO0 to Counter 2 Set count value and start counter Check completion of clock calibration Calibration counter done counter operation Get ILO frequency Figure 23...

  • Page 68: Sample Code For The Initial Configuration Of The Clock Calibration Counter With Ilo0 And Eco Settings

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information Table 32 List of clock calibration counter with ILO0 and ECO settings functions Functions Description Value GetILOClockFreq() Get the ILO 0 frequency. – Cy_SysClk_StartClk Set and start calibration. [Set the counter] MeasurementCounters Clk1: Reference clock...
  • Page 69 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information Code Listing 59 GetILOClockFreq() function uint32_t GetILOClockFreq(void) Check the ECO status. uint32_t counter1 = 40000ul; if((SRSS->unCLK_ECO_STATUS.stcField.u1ECO_OK == 0ul) || (SRSS->unCLK_ECO_STATUS.stcField.u1ECO_READY == 0ul)) while(1); Start the clock measurement counter. See Code Listing cy_en_sysclk_status_t status;...

  • Page 70: Ilo0 Calibration Using The Clock Calibration Counter Function

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information Code Listing 62 Cy_SysClk_ClkMeasurementCountersGetFreq() function if(clk1Count1 == 0ul) return(CY_SYSCLK_INVALID_STATE); Get the ILO 0 count value. volatile uint64_t counter2Value = (uint64_t)SRSS->unCLK_CAL_CNT2.stcField.u24CAL_COUNTER2; /* Done counting; allow entry into DeepSleep mode. */ (6) Get the ILO 0 frequency.

  • Page 71: Configuration

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information 6.2.2.1 Configuration Table 33 lists the parameters and Table 34 lists the functions of the configuration part of in the SDL for ILO0 calibration using clock calibration counter settings. Table 33 List of ILO0 calibration using clock calibration counter settings parameters Parameters...
  • Page 72 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information Code Listing 64 Cy_SysClk_IloTrim() function int32_t Cy_SysClk_IloTrim(uint32_t iloFreq, uint8_t iloNo) /* Nominal trim step size is 1.5% of "the frequency". Using the target frequency. */ const uint32_t trimStep = CY_SYSCLK_DIV_ROUND((uint32_t)CY_SYSCLK_ILO_TARGET_FREQ * 15ul, 1000ul); uint32_t newTrim = 0ul;...

  • Page 73: Csv Diagram And Relationship Of The Monitored Clock And Reference Clocks

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information CSV diagram and relationship of the monitored clock and reference clocks Figure 25 shows the clock diagram with the monitored clock and reference clock of CSV. Table 35 shows the relationship between the monitored clock and reference clock.
  • Page 74 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Supplementary information Table 35 Monitored clock and reference clock CSV components Monitor clock Reference clock Note CSV_HF0 CLK_HF0 CLK_REF_HF CLK_REF_HF is selected from the CLK_IMO, EXT_CLK, CLK_ECO, or CLK_LPECO. CSV_HF1 CLK_HF1 CLK_REF_HF CLK_REF_HF is selected from the CLK_IMO,...

  • Page 75: Glossary

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Glossary Glossary Table 36 Glossary Terms Description AUDIOSS Audio subsystem. See the “Audio subsystem” chapter of TRAVEO™ T2G architecture TRM for details. CAN FD CAN FD is the CAN with flexible data rate, and CAN is the controller area network.
  • Page 76 Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Glossary Terms Description Serial communications block. See the “Serial communications block (SCB)” chapter of the TRAVEO™ T2G architecture TRM for details. SMIF Serial memory interface. See the “Serial memory interface” chapter of the TRAVEO™...

  • Page 77: References

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs References References The following are the TRAVEO™ T2G family series datasheets and technical reference manuals. Contact Technical Support to obtain these documents. [1] Device datasheets: CYT4DN datasheet 32-bit Arm® Cortex®-M7 microcontroller TRAVEO™ T2G family (Doc No. 002-24601) •...

  • Page 78: Other References

    Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs Other references Other references A sample driver library (SDL) including startup as sample software to access various peripherals is provided. The SDL also serves as a reference, to customers, for drivers that are not covered by the official AUTOSAR products.

  • Page 79: Revision History

    Document version 2019-12-12 New application note. 2021-06-07 Updated to Infineon template. 2021-09-07 Updated Configuration of the Clock Resources: Added flowchart and example codes in all instances. Updated Configuration of FLL and PLL: Added flowchart and example codes in all instances.
  • Page 80 Infineon Technologies hereby disclaims dangerous substances. For information on the types © 2021 Infineon Technologies AG. any and all warranties and liabilities of any kind in question please contact your nearest Infineon All Rights Reserved. (including without limitation warranties of non- Technologies office.

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