Use Case; Configuration - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
4.1.2

Use case

Input clock frequency: 16 MHz
•
Output clock frequency: 100 MHz
•
4.1.3

Configuration

Table 7 lists the parameters and
settings.
Table 7 List of FLL settings parameters
Parameters
WAIT_FOR_STABILIZATION
FLL_PATH_NO
FLL_TARGET_FREQ
CLK_FREQ_ECO
PATH_SOURCE_CLOCK_FREQ
CY_SYSCLK_FLLPLL_OUTPUT_
AUTO
Table 8 List of FLL settings functions
Functions
AllClockConfiguration()
Cy_SysClk_FllConfigure
Standard(inputFreq,
outputFreq, outputMode)
Cy_SysClk_FllEnable
(Timeout value)
Cy_SysLib_DelayUs(Wait
Time)
Application Note
Table 8 lists the functions of the configuration part of in the SDL for FLL
Description
Waiting for stabilization
FLL number
FLL target frequency
Source clock frequency
Source clock frequency
FLL output mode
CY_SYSCLK_FLLPLL_OUTPUT_AUTO:
Automatic using the lock indicator.
CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_OR_
NOTHING:
Similar to AUTO, except that the clock is gated
off when unlocked.
CY_SYSCLK_FLLPLL_OUTPUT_INPUT:
Select FLL reference input (bypass mode)
CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT:
Select the FLL output. Ignores the lock
indicator.
See SRSS_CLK_FLL_CONFIG3 in the
TRM for details.
Description
Clock configuration
inputFreq: Input frequency
outputFreq: Output frequency
outputMode: FLL output mode
Set FLL enable and timeout value Timeout value =
Delay by the specified number of
microseconds
27 of 80
10000ul
0u
100000000ul (100 MHz)
16000000ul (16 MHz)
CLK_FREQ_ECO
0ul
registers
Value
–
inputFreq = PATH_SOURCE_
CLOCK_FREQ,
outputFreq = FLL_TARGET_FREQ,
outputMode = CY_SYSCLK_FLLPLL_
OUTPUT_AUTO
WAIT_FOR_STABILIZATION
Wait time = 1u (1us)
Value
002-26071 Rev. *B
2021-09-07