Setting Eco_Prescaler - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.10

Setting ECO_Prescaler

The ECO_Prescaler divides the ECO, and creates a clock that can be used with the CLK_LF. The division function
has a 10-bit integer divider and 8-bit fractional divider.
Figure 19 shows the steps to enable the ECO_Prescaler. For details on the ECO_Prescaler, see the
TRM and registers TRM.
(1)
(2)
(3)
Note: Do not change the ECO_FRAC_DIV and ECO_INT_DIV settings when ECO_DIV_ENABLE = 1.
Figure 19 Enabling the ECO_Prescaler
Figure 20 shows the flow to disable the ECO_Prescaler. For details on the ECO_Prescaler, see the
TRM.
(4)
(5)
Figure 20 Disabling the ECO_Prescaler
Application Note
Start
Define ECO prescaler target frequency
Configure 8-bit fractional value
Configure 10-bit integer value
ECO prescaler enabled
Wait until ECO prescaler is available?
Yes
End
Start
ECO prescaler disabled
Wait until ECO prescaler is unavailable?
Yes
End
Set ECO prescaler target frequency
Configure 8-bit fractional value
Configure 10-bit integer value
ECO prescaler enabled
No
Wait until ECO rescaler is available
ECO prescaler disabled
No
Wait until ECO prescaler is unavailable
57 of 80
architecture
architecture
002-26071 Rev. *B
2021-09-07