Supplementary Information; Input Clocks In Peripheral Functions - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs

Supplementary information

6 Supplementary information
6.1

Input clocks in peripheral functions

Table 23 to Table 30 list the clock input to each peripheral function. For detailed values of PCLK, see the
"Peripheral clocks" section of the datasheet.
Table 23 Clock input to TCPWM[0]
Peripheral function
TCPWM[0]
Table 24 Clock input to CAN FD
Peripheral function
CAN FD0
CAN FD1
Table 25 Clock input to LIN
Peripheral function
LIN
Table 26 Clock input to SCB
Peripheral function
SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7
SCB8
SCB9
SCB10
SCB11
Application Note
Operation clock
CLK_GR3 (Group 3)
Operation clock
(clk_sys (hclk))
CLK_GR5 (Group 5)
Operation clock
CLK_GR5 (Group 5)
Operation clock
CLK_GR6 (Group 6)
Channel clock
PCLK (PCLK_TCPWM0_CLOCKSx, x = 0 to 37)
PCLK (PCLK_TCPWM0_CLOCKSy, y = 256 to 267)
PCLK (PCLK_TCPWM0_CLOCKSz, z =512–543)
Channel clock (clk_can (cclk))
Ch0: PCLK (PCLK_CANFD0_CLOCK_CANFD0)
Ch1: PCLK (PCLK_CANFD0_CLOCK_CANFD1)
Ch0: PCLK (PCLK_CANFD1_CLOCK_CANFD0)
Ch1: PCLK (PCLK_CANFD1_CLOCK_CANFD1)
Channel clock (clk_lin_ch)
Ch0: PCLK (PCLK_LIN_CLOCK_CH_EN0)
Ch1: PCLK (PCLK_LIN_CLOCK_CH_EN1)
Channel clock
PCLK (PCLK_SCB0_CLOCK)
PCLK (PCLK_SCB1_CLOCK)
PCLK (PCLK_SCB2_CLOCK)
PCLK (PCLK_SCB3_CLOCK)
PCLK (PCLK_SCB4_CLOCK)
PCLK (PCLK_SCB5_CLOCK)
PCLK (PCLK_SCB6_CLOCK)
PCLK (PCLK_SCB7_CLOCK)
PCLK (PCLK_SCB8_CLOCK)
PCLK (PCLK_SCB9_CLOCK)
PCLK (PCLK_SCB10_CLOCK)
PCLK (PCLK_SCB11_CLOCK)
65 of 80 002-26071 Rev. *B
2021-09-07