Configuring The Internal Clock; Configuring Clk_Pathx - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs

Configuring the internal clock

5 Configuring the internal clock
This section describes how to configure the internal clocks as part of the clock system.
5.1

Configuring CLK_PATHx

The CLK_PATHx is used as the input source for the root clock, CLK_HFx. The CLK_PATHx can select all clock
resources including the FLL and PLL using DSI_MUX and PATH_MUX. The CLK_PATH9 cannot select the FLL and
PLL, but other clock resources can be selected.
Table 13 shows the relationship between the FLL/PLLs and CLK_PATHx.
Table 13 Relationship between the FLL/PLLs and PATHx
FLL/PLLs
FLL
PLL#0
PLL#1
PLL#2
PLL#3
PLL#4
PLL#5
PLL#6
PLL#7
Directly (FLL and PLL cannot
be selected)
Figure 14 shows a generation diagram for CLK_PATH.
IMO
EXT_CLK
ECO
LPECO
ILO0
PATH_MUX
WCO
ILO1
DSI_MUX
IMO
EXT_CLK
ECO
LPECO
ILO0
PATH_MUX
WCO
ILO1
DSI_MUX
Figure 14 Generation diagram for the CLK_PATH
To configure the CLK_PATHx, you must configure the DSI_MUX and PATH_MUX. The BYPASS_MUX is also
required for the CLK_PATHx.
architecture TRM for details.
Application Note
CLK_PATH0
CLK_PATH1
CLK_PATH2
CLK_PATH3
CLK_PATH4
CLK_PATH5
CLK_PATH6
CLK_PATH7
CLK_PATH8
CLK_PATH9
CLK_PATH0
FLL
BYPASS_SEL
PLL#0/#1/
CLK_PATH1/2/3/4/5
#2/#3/#4
BYPASS_SEL
Table 14 shows the registers required for configuring the CLK_PATHx. See the
CLK_PATHx
IMO
EXT_CLK
ECO
LPECO
ILO0
PATH_MUX
WCO
ILO1
DSI_MUX
IMO
EXT_CLK
ECO
LPECO
ILO0
PATH_MUX
WCO
ILO1
DSI_MUX
48 of 80
PLL#5/ CLK_PATH6/7/8
#6/#7/
BYPASS_SEL
CLK_PATH9
002-26071 Rev. *B
2021-09-07