Configuring The Lpeco_Prescaler; Use Case - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.11

Configuring the LPECO_Prescaler

The LPECO_Prescaler divides the LPECO. The division function has a 10-bit integer divider and 8-bit fractional
divider.
Figure 21 shows the steps to enable the LPECO_Prescaler. For details on the LPECO_Prescaler, see the
architecture TRM.
(1)
(2)
(3)
Note: Do not change the LPECO_FRAC_DIV and LPECO_INT_DIV settings when LPECO_DIV_ENABLE = 1.
Figure 21 Enabling the LPECO_Prescaler
Figure 22 shows the steps to disable the LPECO_Prescaler. For details on the LPECO_Prescaler, see the
architecture TRM.
Figure 22 Disabling the LPECO_Prescaler
5.11.1

Use case

Input clock frequency: 8 MHz
•
LPECO prescaler target frequency: 1.234567 MHz
•
Application Note
Start
Configure 8-bit fractional value
Configure 10-bit integer value
LPECO prescaler enabled
Wait until LPECO prescaler is available?
Yes
End
(4)
LPECO prescaler disabled
(5)
Wait until LPECO prescaler is unavailable?
No
Start
Yes
End
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No
002-26071 Rev. *B
2021-09-07