Example Of Pclk Setting; Use Case; Configuration - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.9.1

Example of PCLK setting

5.9.1.1

Use case

Input clock frequency: 80 MHz
•
Output clock frequency: 2 MHz
•
Divider type: Clock divider 16.0
•
Used divider: Clock divider 16.0#0
•
Peripheral clock output number: 31 (TCPWM0, Group#0, Counter#0)
•
Define TCPWM_PERI_CLK_DIVIDER_NO_COUNTER
(1)
Set input/output frequency and divide number
(2)
(3)
(4)
Figure 18 Example procedure for setting the PCLK
5.9.1.2

Configuration

Table 17 lists the parameters and
PCLK (example of the TCPWM timer) settings.
Table 17 List of PCLK (example of the TCPWM timer) parameters
Parameters
PCLK_TCPWMx_CLOCKSx_
COUNTER
TCPWM_PERI_CLK_DIVIDER_NO
_COUNTER
CY_SYSCLK_DIV_16_BIT
periFreq
Application Note
Start
Define PCLK_TCPWMx_CLOCKSx_COUNTER,
Assign divider to peripheral
Configure the Clock Divider 16.0#0
Enable Clock Divider 16.0#0
End
Table 18 lists the functions of the configuration part of in the SDL for the
PCLK of TCPWM0
Number of dividers to be used
Divider type:
CY_SYSCLK_DIV_8_BIT = 0u, 8 bit divider
CY_SYSCLK_DIV_16_BIT = 1u, 16 bit divider
CY_SYSCLK_DIV_16_5_BIT = 2u, 16.5 bit
fractional divider
CY_SYSCLK_DIV_24_5_BIT = 3u, 24.5 bit
fractional divider
Peripheral clock frequency
Divide number = Input freq/output freq
Clock Divider 16.0#0 assign to
TCPWM0 Group#0 Channel#0
Description
54 of 80
Value
PCLK_TCPWM0_CLOCKS0
= 31ul
0ul
1ul
80000000ul (80 MHz)
002-26071 Rev. *B
2021-09-07