Sample Code For The Initial Configuration Of Fll Settings - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
4.1.4

Sample code for the initial configuration of FLL settings

Code Listing 21 to Code Listing 25
Code Listing 21 General configuration of FLL settings
/** Wait time definition **/
#define WAIT_FOR_STABILIZATION (10000ul)
:
#define FLL_TARGET_FREQ
#define CLK_FREQ_ECO
#define PATH_SOURCE_CLOCK_FREQ CLK_FREQ_ECO
:
#define FLL_PATH_NO
:
int main(void)
{
:
/* Enable interrupt */
__enable_irq();
:
/* Set Clock Configuring registers */
AllClockConfiguration();
:
/* Please check clock output using oscilloscope after CPU reached here. */
for(;;);
}
Code Listing 22 AllClockConfiguration() function
static void AllClockConfiguration(void)
{
:
/***** FLL(PATH0) source setting ******/
{
:
fllStatus = Cy_SysClk_FllConfigureStandard(PATH_SOURCE_CLOCK_FREQ, FLL_TARGET_FREQ, CY_SYSCLK_FLLPLL_OUTPUT_AUTO);
CY_ASSERT(fllStatus == CY_SYSCLK_SUCCESS);
fllStatus = Cy_SysClk_FllEnable(WAIT_FOR_STABILIZATION);
CY_ASSERT((fllStatus == CY_SYSCLK_SUCCESS) || (fllStatus == CY_SYSCLK_TIMEOUT));
:
}
return;
}
Code Listing 23 Cy_SysClk_FllConfigureStandard() function
cy_en_sysclk_status_t Cy_SysClk_FllConfigureStandard(uint32_t inputFreq, uint32_t outputFreq,
cy_en_fll_pll_output_mode_t outputMode)
{
/* check for errors */
if (SRSS->unCLK_FLL_CONFIG.stcField.u1FLL_ENABLE != 0ul)
{
return(CY_SYSCLK_INVALID_STATE);
}
else if ((outputFreq < CY_SYSCLK_MIN_FLL_OUTPUT_FREQ) || (CY_SYSCLK_MAX_FLL_OUTPUT_FREQ < outputFreq))
output frequency */
{
return(CY_SYSCLK_INVALID_STATE);
}
else if (((float32_t)outputFreq / (float32_t)inputFreq) < 2.2f)
{
return(CY_SYSCLK_INVALID_STATE);
}
/* no error */
/* If output mode is bypass (input routed directly to output), then done.
The output frequency equals the input frequency regardless of the frequency parameters. */
if (outputMode == CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
{
/* bypass mode */
/* update CLK_FLL_CONFIG3 register with divide by 2 parameter */
Application Note
show the sample code.
(100000000ul)
(16000000ul)
Define the FLL number.
Define the TIMEOUT variable.
Define the FLL target frequency.
Define the FLL input frequency.
(0ul)
FLL setting. See Code Listing
FLL configuration. See
FLL enable. See
/* 1 = enabled */
Check the FLL output range.
/* check output/input frequency ratio */
Check the FLL frequency ratio.
28 of 80
22.
Code Listing 23.
Code Listing 25.
(1) Check if the FLL is already enabled.
/* invalid
002-26071 Rev. *B
2021-09-07