Use Case; Configuration - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
4.2.1

Use case

Input clock frequency: 16.000 MHz
•
Output clock frequency:
•
250.000 MHz (PLL400 #0)
196.608 MHz (PLL400 #1)
160.000 MHz (PLL200 #0)
80.000 MHz (PLL200 #1)
Fractional divider:
•
Disable (PLL400 #0)
Enable (PLL400 #1)
SSCG:
•
Enable (PLL400 #0)
Disable (PLL400 #1)
SSCG dithering:
•
Enable (PLL400 #0)
Disable (PLL400 #1)
SSCG modulation depth: -2.0% (PLL400)
•
SSCG modulation rate: Divide 512 (PLL400)
•
LF mode: 200 MHz to 400 MHz (PLL200)
•
4.2.2

Configuration

Table 9 and Table 11 list parameters of the PLL (400/200);
(400/200) of the configuration part of in the SDL for PLL (400/200) settings.
Table 9 List of PLL 400 settings parameters
Parameters
PLL400_0_TARGET_FREQ
PLL400_1_TARGET_FREQ
WAIT_FOR_STABILIZATION
PLL400_0_PATH_NO
PLL400_1_PATH_NO
CLK_FREQ_ECO
PATH_SOURCE_CLOCK_FREQ
CY_SYSCLK_FLLPLL_OUTPUT_
AUTO
Application Note
Table 10
Description
PLL400 #0 target frequency
PLL400 #1 target frequency
Waiting for stabilization
PLL400 #0 number
PLL400 #1 number
ECO clock frequency
PATH source clock frequency
FLL output mode
CY_SYSCLK_FLLPLL_OUTPUT_AUTO:
Automatic using the lock indicator
CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_OR_
NOTHING:
Similar to AUTO, except that the clock is gated
off when unlocked
CY_SYSCLK_FLLPLL_OUTPUT_INPUT:
Selects the FLL reference input (bypass mode)
CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT:
33 of 80
and Table 12 list functions of the PLL
250 MHz (250000000ul)
196.608 MHz
(196608000ul)
10000ul
1u
2u
16000000ul (16 MHz)
CLK_FREQ_ECO
0ul
Value
002-26071 Rev. *B
2021-09-07