Use Case; Configuration - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.10.1

Use case

Input clock frequency: 16 MHz
•
ECO prescaler target frequency: 1.234567 MHz
•
5.10.2

Configuration

Table 19 lists the parameters and
prescaler settings.
Table 19 List of ECO prescaler settings parameters
Parameters
ECO_PRESCALER_TARGET_FREQ ECO prescaler target frequency
WAIT_FOR_STABILIZATION
CLK_FREQ_ECO
PATH_SOURCE_CLOCK_FREQ
Table 20 List of ECO prescaler setting functions
Functions
AllClockConfiguration()
Cy_SysClk_SetEco
Prescale(Inclk, Targetclk)
Cy_SysClk_EcoPrescale
Enable(Timeout value)
Cy_SysClk_SetEco
PrescaleManual (divInt,
divFact)
Cy_SysClk_GetEco
PrescaleStatus
Application Note
Table 20 lists the functions of the configuration part of in the SDL for ECO
Description
Waiting for stabilization
ECO clock frequency
PATH source clock frequency
Description
Clock configuration
Set the ECO frequency and
target frequency.
Set the ECO prescaler
enable and timeout value
divInt: 10-bit integer value
allows for ECO frequencies
divFrac: 8-bit fractional
value
Check the prescaler status. –
58 of 80
1234567ul
10000ul
16000000ul (16 MHz)
CLK_FREQ_ECO
Value
–
Inclk = PATH_SOURCE_CLOCK_FREQ,
Targetclk =
ECO_PRESCALER_TARGET_FREQ
Timeout value = WAIT_FOR_STABILIZATION
–
Value
002-26071 Rev. *B
2021-09-07