Sample Code For The Initial Configuration Of Pclk Settings (Example Of The Tcpwm Timer) - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
Parameters
targetFreq
divNum
Table 18 List of PCLK (Example of the TCPWM timer) settings functions
Functions
Cy_SysClk_PeriphAssign
Divider(IPblock,
dividerType, dividerNum)
Cy_SysClk_PeriphSet
Divider(dividerType,
dividerNum, dividerValue)
Cy_SysClk_PeriphEnable
Divider(dividerType,
dividerNum)
5.9.2 Sample code for the initial configuration of PCLK settings (example of
the TCPWM timer)
Code Listing 40 to Code Listing 43
Code Listing 40 General configuration of PCLK (example of the TCPWM timer) settings
:
#define PCLK_TCPWMx_CLOCKSx_COUNTER
#define TCPWM_PERI_CLK_DIVIDER_NO_COUNTER 0u
:
int main(void)
{
SystemInit();
__enable_irq(); /* Enable global interrupts. */
uint32_t periFreq = 80000000ul;
uint32_t targetFreq = 2000000ul;
uint32_t divNum = (periFreq / targetFreq);
CY_ASSERT((periFreq % targetFreq) == 0ul);
Cy_SysClk_PeriphAssignDivider(PCLK_TCPWMx_CLOCKSx_COUNTER, CY_SYSCLK_DIV_16_BIT,
TCPWM_PERI_CLK_DIVIDER_NO_COUNTER);
/* Sets the 16-bit divider */
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, TCPWM_PERI_CLK_DIVIDER_NO_COUNTER, (divNum-1ul));
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, TCPWM_PERI_CLK_DIVIDER_NO_COUNTER);
for(;;);
}
Application Note
Description
Target clock frequency
Divide number
Description
Assign a programmable
divider to a selected IP block
(such as a TCPWM)
Set the peripheral divider
Enable the peripheral
divider
show the sample code.
PCLK_TCPWM0_CLOCKS0
Calculation of division
// inaccurate target clock
Peripheral divider enable setting. See
Code Listing
55 of 80
IPblock =
PCLK_TCPWMx_CLOCKSx_COUNTER
dividerType = CY_SYSCLK_DIV_16_BIT
dividerNum =
TCPWM_PERI_CLK_DIVIDER_NO_COUNTER
dividerType, = CY_SYSCLK_DIV_16_BIT
dividerNum =
TCPWM_PERI_CLK_DIVIDER_NO_COUNTER
dividerValue = divNum-1ul
dividerType, = CY_SYSCLK_DIV_16_BIT
dividerNum =
TCPWM_PERI_CLK_DIVIDER_NO_COUNTER
Define PCLK_TCPWMx_CLOCKSx_COUNTER,
Define TCPWM_PERI_CLK_DIVIDER_NO_COUNTER.
/output frequency and divide number.
(1) Set the input
Peripheral divider assign setting. See
Code Listing
Peripheral divider setting. See
43. Listing
Value
2000000ul (2 MHz)
periFreq/targetFreq
Value
41.
Code
42.
002-26071 Rev. *B
2021-09-07