Use Case Of The Clock Calibration Counter Function - Infineon TRAVEO T2G family CYT4D Series Manual

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Supplementary information
Table 27 Clock input to SAR ADC
Peripheral function
SAR ADC
Table 28 Clock input to CXPI
Peripheral function
CXPI
Table 29 Clock input to SMIF
Peripheral function
SMIF
Table 30 Clock input to AUDIOSS
Peripheral function
AUDIOSS
Note: For details on Ethernet clocks, see the
6.2

Use case of the clock calibration counter function

The clock calibration counter has two counters that can be used to compare the frequency of two clock
sources. All clock sources are available as a source for these two clocks. For details, see the
Use the following procedure to calibrate using the clock calibration counter:
Calibration Counter1 counts clock pulses from Calibration Clock1 (the high-accuracy clock used as the
1.
reference clock). It counts downwards.
Calibration Counter2 counts clock pulses from Calibration Clock2 (measurement clock). It counts upwards.
2.
When Calibration Counter1 reaches 0, Calibration Counter2 stops counting upwards, and its value can be
3.
read.
The frequency of Calibration Counter2 can be obtained by using its value and the following equation:
4.
Figure 23 shows an example of the clock calibration counter function when ILO0 and ECO are used. ILO0 and
ECO must be enabled. See ILO0 and ECO for
Application Note
Operation clock
CLK_GR9 (Group 9)
Operation clock
CLK_GR5 (Group 5)
"clk_slow" domain
(XIP AHB-Lite
Interface0) (XIP AHB interface)
clk_slow clk_mem
clk_sys_i2s
CLK_HF5
Counter2value
CalibrationClock2 =
Counter1value
3.4 Configuring ILO0/ILO1
Unit0: PCLK (PCLK_PASS_CLOCK_SAR0)
Channel clock
PCLK (PCLK_CXPI0_CLOCK_CH_EN0)
PCLK (PCLK_CXPI0_CLOCK_CH_EN1)
"clk_mem" "clk_sys" domain
Domain
(MMIO AHB-Lite
CLK_GR4
CLK_GR8
architecture TRM.
× CalibrationClock1
and
66 of 80
Unit clock
"clk_if" domain
interface)
CLK_HF6
clk_audio_i2s
architecture
3.1 Setting the ECO.
002-26071 Rev. *B
TRM.
2021-09-07