ON Semiconductor ADT7476AARQZ-R Manual page 53

Table 52. VOLTAGE READING REGISTERS (POWER-ON DEFAULT = 0x00)
Register Address
0x20
0x21
0x22
0x23
0x24
1. If the extended resolution bits of these readings are also being read, the extended resolution registers (Register 0x76, Register 0x77) must
be read first. Once the extended resolution registers have been read, the associated MSB reading registers are frozen until read. Both the
extended resolution registers and the MSB registers are frozen.
2. If V Low (Bit 7 of 0x40) is set, V
CCP
3. V (Pin 4) is the supply voltage for the ADT7476A.
CC
Table 53. TEMPERATURE READING REGISTERS (POWER-ON DEFAULT = 0x80)
Register Address
0x25
0x26
0x27
1. If the extended resolution bits of these readings are also being read, the extended resolution registers (Register 0x76, Register 0x77) must
be read first. Once the extended resolution registers have been read, all associated MSB reading registers are frozen until read. Both the
extended resolution registers and the MSB registers are frozen.
2. These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration
Register 5 (0x7C).
3. In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel.
4. In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel.
Table 54. FAN TACHOMETER READING REGISTERS (POWER-ON DEFAULT = 0x00)
Register Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
1. These registers count the number of 11.11 ms periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH
pulses (default = 2). The number of TACH pulses used to count can be changed using the TACH Pulses per Revolution register (Register 0x7B).
This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes be read, the low byte must
be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until the first valid fan TACH
measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF
indicates that a fan is one of the following: stalled or blocked (object jamming the fan), failed (internal circuitry destroyed), or not populated. (The
ADT7476A expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should
be set to 0xFFFF.) An alternate function, for example, is TACH4 reconfigured as the THERM pin.
Table 55. CURRENT PWM DUTY CYCLE REGISTERS (POWER-ON DEFAULT = 0xFF)
Register Address
0x30
0x31
0x32
1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7476A
reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed
control mode. During fan startup, these registers report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle
value by writing to these registers.
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R/W
Read-only Reflects the Voltage Measurement at the 2.5 V Input on Pin 22 (8 MSBs of Reading)
Read-only
Reflects the Voltage Measurement (Note 2) at the V
Read-only
Reflects the Voltage Measurement (Note 3) at the V
Read-only Reflects the Voltage Measurement at the 5.0 V Input on Pin 20 (8 MSBs of Reading)
Read-only Reflects the Voltage Measurement at the 12 V Input on Pin 21 (8 MSBs of Reading)
can control the sleep state of the ADT7476A.
CCP
R/W
Read-only Remote 1 Temperature Reading (Note 3 and 4) (8 MSBs of Reading)
Read-only Local Temperature Reading (8 MSBs of Reading)
Read-only Remote 2 Temperature Reading (Note 3 and 4) (8 MSBs of Reading)
R/W
Read-only TACH1 Low Byte
Read-only TACH1 High Byte
Read-only TACH2 Low Byte
Read-only TACH2 High Byte
Read-only TACH3 Low Byte
Read-only TACH3 High Byte
Read-only TACH4 Low Byte
Read-only TACH4 High Byte
R/W
R/W PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
R/W PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
R/W PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
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ADT7476A
(Note 1)
Description
CCP
CC
Description
Description
Description
53
Input on Pin 23 (8 MSBs of Reading)
Input on Pin 4 (8 MSBs of Reading)
(Note 1. 2 and 3)
(Note 1)
(Note 1)