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THERM Timer
The ADT7476A has an internal timer to measure THERM
assertion time. For example, the THERM input can be
connected to the PROCHOT output of a Pentium
measure system performance. The THERM input can also
be connected to the output of a trip-point temperature sensor.
The timer is started on the assertion of the ADT7476A's
THERM input and stopped when THERM is de-asserted.
The timer counts THERM times cumulatively; that is, the
timer resumes counting on the next THERM assertion. The
THERM timer continues to accumulate THERM assertion
times until the timer is read (where it is cleared), or until it
reaches full scale. If the counter reaches full scale, it stops
at that reading until cleared.
The 8-bit THERM timer status register (0x79) is designed
so that Bit 0 is set to 1 on the first THERM assertion. Once
the cumulative THERM assertion time has exceeded
45.52 ms, Bit 1 of the THERM timer is set and Bit 0 now
becomes the LSB of the timer with a resolution of 22.76 ms
(see Figure 32).
THERM
THERM
TIMER
(REG. 0x79)
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
Figure 32. Understanding the THERM Timer
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0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
THERM ASSERTED
≤22.76 ms
0
0
0
0
0
0
1
0
7
6
5
4
3
2
1
0
THERM ASSERTED
≥45.52 ms
0
0
0
0
0
1
0
1
7
6
5
4
3
2
1
0
THERM ASSERTED
≥113.8 ms
(91.04 ms + 22.76 ms)
ADT7476A
When using the THERM timer, be aware of the following:
After a THERM timer read (0x79)
1. The contents of the timer are cleared on read.
®
4 CPU to
2. The F4P bit (Bit 5) of Interrupt Status Register 2
needs to be cleared (assuming that the THERM
timer limit has been exceeded).
If the THERM timer is read during a THERM assertion, the
following occurs:
1. The contents of the timer are cleared.
2. Bit 0 of the THERM timer is set to 1, because a
THERM assertion is occurring.
3. The THERM timer increments from zero.
4. If the THERM timer limit register (0x7A) = 0x00,
the F4P bit is set.
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7476A can generate SMBALERTs when a
programmable THERM timer limit has been exceeded. This
allows the system designer to ignore brief, infrequent
THERM assertions, while capturing longer THERM timer
events. Register 0x7A is the THERM timer limit register.
This 8-bit register allows a limit from 0 sec (first THERM
assertion) to 5.825 sec to be set before an SMBALERT is
generated. The THERM timer value is compared with the
contents of the THERM timer limit register. If the THERM
timer value exceeds the THERM timer limit value, then the
F4P bit (Bit 5) of Interrupt Status Register 2 is set and an
SMBALERT is generated.
NOTE: Depending on which pins are configured as a THERM timer,
setting the F4P bit (Bit 5) of Mask Register 2 (0x75) or Bit 0
of Mask Register 1 (0x74) masks out SMBALERT; although
the F4P bit of Interrupt Status Register 2 is still set if the
THERM timer limit is exceeded.
Figure 33 is a functional block diagram of the THERM
timer, limit, and associated circuitry. Writing a value of 0x00
to the THERM timer limit register (0x7A) causes an
SMBALERT to be generated on the first THERM assertion.
A THERM timer limit value of 0x01 generates an
SMBALERT once cumulative THERM assertions exceed
45.52 ms.
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