Download Print this page

ON Semiconductor ADT7476AARQZ-R Manual page 24

Remote thermal controller and voltage monitor

Advertisement

Table 30. INTERRUPT MASK REGISTER 1 (0x74)
Bit
Mnemonic
[7]
OOL
[6]
R2T
[5]
LT
[4]
R1T
[3]
5.0 V
[2]
V
CC
[1]
V
CCP
[0]
2.5 V
Table 31. INTERRUPT MASK REGISTER 2 (0x75)
Bit
Mnemonic
[7]
D2
[6]
D1
[5]
FAN4
[4]
FAN3
[3]
FAN2
[2]
FAN1
[1]
OVT
[0]
12 V/VC
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by
default. Pin 10 or Pin 14 can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
Table 32. CONFIGURING PIN 10 AS SMBALERT
OUTPUT
Register
Configuration Register 3
(0x78)
Assigning THERM Functionality to a Pin
Pin 14 on the ADT7476A has four possible functions:
SMBALERT, THERM, GPIO6, and TACH4. The user
chooses the required functionality by setting Bit 0 and Bit 1
of Configuration Register 4 (0x7D).
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Arrow.com.
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Description
1 masks SMBALERT for any alert
condition flagged in Interrupt Status
Register 2.
1 masks SMBALERT for Remote 2
temperature.
1 masks SMBALERT for Local
temperature.
1 masks SMBALERT for Remote 1
temperature.
1 masks SMBALERT for the 5.0 V
channel.
1 masks SMBALERT for the V
CC
channel.
1 masks SMBALERT for the V
CCP
channel.
1 masks SMBALERT for the
2.5 V
/THERM channel.
IN
Description
1 masks SMBALERT for Diode 2 errors.
1 masks SMBALERT for Diode 1 errors.
1 masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the
THERM input, this bit masks
SMBALERT for a THERM event. If the
TACH4 pin is being used as GPIO6,
setting this bit masks interrupts related
to GPIO6.
1 masks SMBALERT for Fan 3.
1 masks SMBALERT for Fan 2.
1 masks SMBALERT for Fan 1.
1 masks SMBALERT for
overtemperature (exceeding THERM
limits).
1 masks SMBALERT for 12 V channel
or for a VID code change, depending on
the function used.
Bit Setting
[1] Pin 10 = SMBALERT
[0] Pin 10 = PWM2
ADT7476A
If THERM is enabled on Bit 1, Configuration Register 3
(0x78):
Pin 22 becomes THERM.
If Pin 14 is configured as THERM on Bit 0 and Bit 1 of
Configuration Register 4 (0x7D), THERM is enabled
on this pin.
If THERM is not enabled:
Pin 22 becomes a 2.5 V measurement input.
If Pin 14 is configured as THERM, then THERM is
disabled on this pin.
Table 33. CONFIGURING PIN 14
Bit 1
0
0
1
1
THERM as an Input
When THERM is configured as an input, the user can time
assertions on the THERM pin. This can be useful for
connecting to the PROCHOT output of a CPU to gauge
system performance.
When the THERM pin is driven low externally, the user
can also set up the ADT7476A to run the fans at 100%. The
fans run at 100% for the duration of time that the THERM
pin is pulled low. This is done by setting the BOOST bit
(Bit 2) in Configuration Register 3 (0x78) to 1. This works
only if the fan is already running, for example, in manual
mode, when the current duty cycle is above 0x00, or in
automatic mode when the temperature is above T
If the temperature is below T
manual mode is set to 0x00, pulling the THERM low
externally has no effect. See Figure 31 for more information.
T
MIN
THERM
THERM ASSERTED TO LOW AS
AN INPUT: FANS DO NOT GO
TO 100% BECAUSE TEMPERATURE
IS BELOW T
MIN
Figure 31. Asserting THERM Low as an Input in
Automatic Fan Speed Control Mode
www.onsemi.com
24
Bit 0
Function
0
TACH4
1
THERM
0
SMBALERT
1
GPIO6
.
MIN
or if the duty cycle in
MIN
THERM ASSERTED TO LOW AS
AN INPUT: FANS GO TO 100%
BECAUSE TEMPERATURE IS
ABOVE T
AND FANS ARE
MIN
ALREADY RUNNING.

Advertisement

loading