Sony BCU-100 Maintenance Manual page 23

8) EEPROM
Two 256 Kbit EEPROM (IC6587-8) are mounted.
The SYSCON log, error history, and other data is
recorded here.
4. Reset circuit
The voltage monitoring chip (IC6008) monitors the voltage
of V3P3_MAIN that acts as the power supply for the
SYSCON circuit. The reset signal generated by this chip
performs hard reset on the SYSCON (IC6005). This
mechanism initializes predetermined areas over the entire
SYSCON.
The hardware reset switch (SW6001) is located on the BE
board. Pressing this switch performs reset on the entire
system, but this method is normally not used. When this
switch is pressed, all of the power supplies supplied to
each device are switched off all at once instead of switch-
ing off in order. This can cause massive damage to the
device, particularly if it occurs during operations. On the
other hand, the reset switch on the front panel is a software
reset for SYSCON and can be sued when the unit falls into
a critical state such as hang-up. The SYSCON (IC6005) is
notified through the IO port that the switch has been
pressed and applies reset to the entire system (see the reset
system diagram).
5. Clock circuit
The main clock system is based on the crystal oscillating
circuit (14.31818 MHz) of the master clock generator
(IC5601) and it generates the required clock with three
PLL chips and chip built-in PLL. A local crystal oscillator
or oscillating circuit may also be included on each type of
chip (see the clock system diagram).
(1) Master Clock Generator
ICS1493 (IC5601) : Generates the following clock
from the original oscillations from the 14.31818 MHz
crystal oscillating circuit.
. RSX_PLL_REFCLK : 100 MHz
. SB_PEX0_REFCLK : 100 MHz
. SB_PEX_REFCLK : 100 MHz
. SB_PCI_CLK : 33 MHz
. SB_SYSCLK : 66 MHz
. MK_ATA_CLK : 133 MHz
(2) XCG0 for BE core
ICS9218 (IC5010) : Generates the following clock
from the 100 MHz Master Clock Generator.
. BE_PLL_REF_CLK : 400 MHz
(3) XCG2 for IOIF
ICS9214 (IC5003) : Generates the following clock
from the 100 MHz Master Clock Generator.
BCU-100 MM
. BE_RC_REFCLK : 500 MHz
. RSX_RC_REFCLK : 500 MHz
. SB_RC_REFCLK : 500 MHz
(4) XCG3 for XDR Memory
ICS9218 (IC5012) : Generates the following clock
from the 100 MHz Master Clock Generator.
. BE_Y0_RQ_CTM : 400 MHz
. BE_Y1_RQ_CTM : 400 MHz
(5) Power supply supplied to the clock system
The following are the required power supplies for the
clock circuit.
. V3P3_MK_VDD : IC7502
. V2P5_LREG_XCG_500 : IC7503
. V2P5_LREG_XCG_500_MEM : IC7504
6. FAN
Using the thermal diode in the Cell/B.E. or RSX chip or
the thermal sensor positioned on the BE board, the temper-
ature in the set is sensed and the SYSCON controls are
used to control the fan to three rotation speeds in order to
manage the internal temperature of the set. The fan is a
PWM control fan, so the chip controlling each fan releases
a signal according to controls from the SYSCON, and the
PWM signal corresponding to that control is input into
each fan. The fan rotates at the rotation speed that corre-
sponds to the PWM signal. The fan is 40 mm square and
has a maximum rotation speed of 14,000 rpm. By using
this small size, large air volume fan, the temperature can
be controlled easily.
(1) Cell/B.E. temperature management
The temperature sensing IC (IC6133) uses the thermal
diode in the Cell/B.E. to sense the temperature inside
the chip and simultaneously senses temperature data
around the sensing IC. The temperature is managed on
the Cell/B.E. from SYSCON controls based on this
data.
(2) RSX temperature management
The temperature sensing IC (IC6134) uses the thermal
diode in the RSX to sense the temperature inside the
RSX and simultaneously senses temperature data
around the sensing IC. The temperature is managed on
the RSX from SYSCON controls based on this data.
(3) Memory extension adapter (BKCU-EX1) temperature
management
A temperature sensor is also placed on the MEM-122/
MEM-126 board. The temperature is controlled by
reading this data as the status of the memory extension
adapter.
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