Circuit Description - Sony BCU-100 Maintenance Manual

1-8. Circuit Description

1-8-1. BCU-100
BCU-100 is composed of the following six types of boards
plus the hard disc drive, fan, and power supply unit.
Used boards
. BE-28 board : Main board (Major components such as
Cell/B.E., RSX, and SCC are mounted)
. KY-631 board : Board for operations and display
systems installed on the front panel. It
includes RS-232C connector and
MAINTENANCE connector as external
I/O.
. LED-471 board : Message LED board
. CN-3056 board : Connector board for releasing HDD
. EX-1076 board : PCI-Express extension board. Connects
to the memory extension adapter
(BKCU-EX1).
. RE-255 board : DC/DC board that generates +5 V and
+3.3 V from the +12 V output from the
power supply unit.
BE-28 board
1. Major chip
A core is constructed on the BE-28 board by mounting
four types of cutting-edge chips, connecting the chips to
each other with high-speed signal wires, and realizing high
performance data process abilities for BCU-100.
(1) Cell/B.E. : main processor
Main processor that realizes high-speed data process-
ing for BCU-100.
. XIO
Connecting to the XDR DRAM used as main
memory enables high-speed data transfer. The Cell/
B.E. chip has two systems of 4 byte ports and the
transfer clock for data is 400 MHz. Eight pieces of
data can be transferred with each clock (Octal Data
Rate:ODR), so each port provides speed of 12.8
GByte/sec (400 MHz x 8 ODR x 4 Byte).
. IOIF (FlexIO)
This is the interface for the graphic processor RSX
and peripheral controller SCC. With one byte as one
lane, it achieves transfer speeds of 5 GByte/sec at
full rate and 2.5 GByte/sec at half rate. The transfer
speeds are different to RSX and to SCC as shown
below:
. Cell/B.E. to RSX : 4 lane (20 GB/sec)
. RSX to Cell/B.E. : 3 lane (15 GB/sec)
. Cell/B.E. to SCC : 1 lane (5 GB/sec)
. SCC to Cell/B.E. : 1 lane (5 GB/sec)
1-12 (E)
. Clock
There are two types of clock signals input to the
Cell/B.E. chip. The chip internally operates at 8
times the 400 MHz clock of BE_PLL_REFCLK for
a speed of 3.2 GHz.
. Core reference clock :
BE_PLL_REFCLK (400 MHz)
. IO reference clock : BE_RC_REFCLK (500 MHz)
. Power system
. Core
V1P0_BE_VDDC : Main power supply for the core
main processor.
The main power for the Cell/B.E. is supplied from
here.
Controller : NCP5318(IC7100)
Switching device : IP2003A (IC7101, 7102, 7103)
. VCS
V1P2_BE_VCS : Sub power supply for the CELL
chip core.
Controller : SN105233DBTR (IC7400)
. Clock
V1P5_BE_TERMAL_VDDA : Power supply for
PLL and thermal sensor.
. XIO
V1P5_LREG_BE_YC_VDDA : Power supply for
interface for XDR memory.
. FlexIO
V1P5_LREG_BE_RC_VDDA : Power supply for
interface FlexIO for RSX and SCC.
(2) RSX : Graphic processor
Graphic processor that realizes high speed processing
for BCU-100 along with Cell/B.E. for the main
processor.
. Clock
. Core reference clock :
RSX_PLL_REFCLK (100 MHz)
. IO reference clock : RSX_RC_REFCLK (500 MHz)
. Power system
. Core
V1P2_RSX_VDDC : Main power supply for core
. GDDR
V1P8_RSX_FBVDD :
Power supply for graphic memory
. Clock
V1P8_RSX_PLL_VDD :
Power supply for clock system
. FlexIO
V1P5_LREG_RSX_RC_VDD :
Power supply for FlexIO
BCU-100 MM