JYTEK PXIe-69529 User Manual

JYTEK PXIe-69529 User Manual

8-ch 24-bit 204.8 ks/s dynamic signal acquisition module
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PXIe-69529
8-CH 24-Bit 204.8 kS/s
Dynamic Signal Acquisition Module
User's Manual
Manual Rev.: 1 .00
Revision Date: Jul.16,2016

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Summary of Contents for JYTEK PXIe-69529

  • Page 1 PXIe-69529 8-CH 24-Bit 204.8 kS/s Dynamic Signal Acquisition Module User’s Manual Manual Rev.: 1 .00 Revision Date: Jul.16,2016...
  • Page 2: Getting Service

    Getting Service Contact us should you require any service or assistance. SHANGHAI JYTEK Co., Ltd. Web site: http://www.jytek.com Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203 China Tel: +86-21-5047-5899 Fax: +86-21-5047-5899 Email: service@jytek.com Additional information, aids, and tips that help users perform tasks Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
  • Page 3: Table Of Contents

    Table of Contents Getting Service �������������������������������������������������������������������������������������������������� I 1 Introduction ������������������������������������������������������������������������������������������������ 1 1�1 Features ��������������������������������������������������������������������������������������������� 1 1.2 Applications ��������������������������������������������������������������������������������������� 1 1.3 Specifications ������������������������������������������������������������������������������������� 2 1�3�1 Analog Input ��������������������������������������������������������������������������� 2 1�3�2 Timebase �������������������������������������������������������������������������������� 4 1�3�3 Triggers ����������������������������������������������������������������������������������� 4 1.3.4 General Specifications ������������������������������������������������������������� 4 1.4 Software Support �������������������������������������������������������������������������������...
  • Page 5 List of Tables Table 1-1: Channel Characteristics �������������������������������������������������������������������� 2 Table 1-2: Timebase ����������������������������������������������������������������������������������������� 4 Table 1-3: Trigger Source & Mode �������������������������������������������������������������������� 4 Table 1-4: Digital Trigger Input ������������������������������������������������������������������������� 4 Table 3-1: Input Range and Data Format ���������������������������������������������������������11 Table 3-2: Input Range Midscale Values ����������������������������������������������������������12 Table 3-3: ADC Sample Rates vs DDS Output Clock ������������������������������������������12 Table 3-4: Preferred Characteristics for Analog Triggers �����������������������������������16 Table 3-5: Timing Relationship between ADC and PLL Clock ����������������������������18...
  • Page 6 Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp ������������������������������������ 3 Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp ��������������������������������������� 3 Figure 1-3: PXIe-69529 schematic ��������������������������������������������������������������������� 6 Figure 1-4: PXIe-69529 I/O Array ����������������������������������������������������������������������� 7 Figure 3-1: Analog Input Architecture ��������������������������������������������������������������10 Figure 3-2: Linked List of PCI Address DMA Descriptors ������������������������������������13 Figure 3-3: Trigger Architecture������������������������������������������������������������������������14...
  • Page 7: Introduction

    1 Introduction The PXIe-69529 is a high-performance 8-CH 24-Bit 204.8 kS/s dynamic signal acquisition module, specifically designed for applications such as structural health monitoring, noise, vibration, and harshness (NVH) measurement, and phased array data acquisition. The PXIe-69529 features 24-bit simultaneous sampling at 204.8 kS/s over 8 channels, and a 110 dB dynamic range, providing ample power for high-density, high channel count signal measurement, and vibration-optimized lower AC cutoff frequency of 0.3 Hz.
  • Page 8: Specifications

    1�3 Specifications 1�3�1 Analog Input Channel Characteristics Comment Channels Type Differential or Pseudo-Differential Coupling AC or DC, software selectable AC coupling cutoff frequency 0.5Hz ADC resolution 24-Bit ADC type Delta-sigma Input signal range ±10V, ±1V Sampling rate (fs) 8 kS/s to 204.8 kS/s, 768 μS/s increments for fs >...
  • Page 9: Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp

    Magnitude Response −5 −10 −15 −20 −25 Frequency (Hz) x 10 Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp Response when AC coupling enabled −2 −4 −6 −8 −10 −12 Frequency (Hz) Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp...
  • Page 10: 1�3�2 Timebase

    1�3�2 Timebase Sampling Clock Timebase options Internal: onboard synthesizer External: PXI_CLK10, PXIe_CLK100 Timebase accuracy < ± 25ppm Table 1-2: Timebase 1�3�3 Triggers Trigger Source & Mode Trigger source Software, external digital trigger, analog trigger, PXI trigger bus[0..7], PXI_STAR, and PXIe_DSTARB Trigger mode Post trigger and delay trigger Table 1-3: Trigger Source &...
  • Page 11: Software Support

    Windows operating systems. The development environment may be VB, VB.NET, VC++, BCB, and Delphi, or any Windows programming language that allows calls to a DLL. The DSA-DASK user and function reference manuals are on the JYTEK website (www.jytek.com).
  • Page 12: 1�5 Device Layout And I/O Array

    1�5 Device Layout and I/O Array All dimensions are in mm. Figure 1-3: PXIe-69529 schematic...
  • Page 13: Figure 1-4: Pxie-69529 I/O Array

    The PXIe-69529 I/O array is labeled to indicate connectivity, as shown. Figure 1-4: PXIe-69529 I/O Array...
  • Page 14: Getting Started

    • Anti-static wrist strap • Antistatic mat JYTEK PXIe-69529 DSA modules are electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.
  • Page 15: 2�2 Installing The Module

    2�2 Installing the Module 1. Turn off the PXI system/chassis and disconnect the power cable from the power source. 2. Align the module edge with the module guide in the PXI chassis. 3. Slide the module into the chassis until resistance is felt from the PXI connector. 4.
  • Page 16: Operations

    Figure 3-1: Analog Input Architecture Differential and Pseudo-Differential Input Configuration The PXIe-69529 provides both differential and psuedo-differential input configurations, with differential input mode providing voltage to the anode and cathode inputs of the SMB connector according to signal voltage difference therebetween. If the signal source is...
  • Page 17: 3�2�2 Input Range And Data Format

    Following completion of A/D conversion, A/D data is buffered in a Data FIFO, and can then be transferred to PC memory for further processing. Transfer characteristics of the two input ranges of the PXIe-69529 are as follows. Data format of the PXIe-69529 is 2’s complement.
  • Page 18: 3�2�3 Adc And Analog Input Filter

    3�2�4 DMA Data Transfer The PXIe-69529, as a PCIe Gen1 X 4 device, provides a 204.8 KS/s sampling rate ADC, generating a 3.276 MByte/second rate. To provide efficient data transfer, a PCI bus- mastering DMA is essential for continuous data streaming, as it helps to achieve the full potential PCI Express bus bandwidth.
  • Page 19: Figure 3-2: Linked List Of Pci Address Dma Descriptors

    After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA. In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or other, it is difficult to allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with scatter-gather function to link non-contiguous memory blocks into a linked list to enable transfer of large amounts of data without memory limitations.
  • Page 20: 3�3 Trigger Source And Trigger Modes

    3�3 Trigger Source and Trigger Modes Figure 3-3: Trigger Architecture The PXIe-69529 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PXIe-69529 supports internal software trigger, external digital trigger, PXI_STAR trigger, PXIe_DSTARB, PXI Trigger Bus [0.7], and SSI bus as well as analog trigger.
  • Page 21 When configured as input, the PXIe-69529 serves as a slave module and can accept trigger signals from one of buses 0 through 7. When configured as output, the PXIe-69529 serves as a master module and can output trigger signals to the PXI Trigger Bus Numbers 0 through 7.
  • Page 22: 3�4 Trigger Mode

    Table 3-4: Preferred Characteristics for Analog Triggers Trigger Export The PXIe-69529 can export trigger signals to PXI Trigger Bus Numbers 0 through 7, utilizing them to act as the System Synchronization Interface. When configured as the output, the PXIe-69529 serves as a master module and can output trigger signals to synchronize the slave modules, with the trigger signal routed to any of the seven PXI Trigger Bus Numbers via software.
  • Page 23: Figure 3-6: Post-Trigger Acquisition

    Post Trigger Mode If post trigger mode is configured, activity commences once the following trigger conditions are met: • The analog input channel acquires a programmed number of samples at a specified sampling rate • The analog output channel outputs pre-defined voltage at a specified output rate Figure 3-6: Post-Trigger Acquisition Delay Trigger Mode If delay trigger mode is configured, delay time from when the trigger event asserts to the...
  • Page 24: 3�5 Adc Timing Control

    period of PCIe CLK. After the initial setup, no additional software intervention is required. Operation 1st Trigger Event Occurs 2nd Trigger Event Occurs start Time Trigger Data N samples N samples Figure 3-8: Re-Trigger Mode Acquisition 3�5 ADC Timing Control 3�5�1 Timebase Figure 3-9: Timebase Architecture An onboard timebase clock drives the sigma-delta ADC, with frequency exceeding the...
  • Page 25: 3�5�3 Filter Delay In Adc

    The eight interconnected lines on the PXI Express backplane, labeled PXI Trigger Bus[0:7] provide a flexible interface for syncing multiple modules. The PXIe-69529 utilizes the PXI Trigger Bus [0:7] as a System Synchronization Interface (SSI). Flexible routing of timebase clock and trigger signals onto the PXI Trigger Bus enables the PXIe-69529 to simplify synchronization between multiple modules.The bidirectional SSI I/O...
  • Page 26: Ssi_Timebase

    PXI trigger bus achieving synchronization on the three timing signals, as follows. 3.6.1 SSI_TIMEBASE As output, the SSI_TIMEBASE signal transmits the onboard ADC timebase through the PXI trigger bus. As input, the PXIe-69529 accepts the SSI_TIMEBASE signal as the source of the timebase. 3�6�2 SSI_SYNC_START Before a SSI master issues SSI_TRIG to other SSI slaves, SSI_SYNC_START is first asserted by the master card, synchronizing all on-chip ADCs in both SSI Master and SSI Slave modules.
  • Page 27: Appendix A Calibration

    A�1 Calibration Constant The PXIe-69529 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PXIe-69529 driver loads these calibration constants, such that analog input path errors are minimized. JYTEK provides a software API for calibrating the PXIe-69529.
  • Page 28: Important Safety Instructions

    Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. • Read these safety instructions carefully. • Keep this user’s manual for future reference. •...

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