Design Example : Cs8900 Interface To Mc68302; Address Generation - Cirrus Logic CRYSTAL LAN CS890 Technical Reference Manual

MC68302
UDS*/A0
A[1:11]
A12
CS1*
R/W*
Interrupt
Controller
INT*
Figure 5.1 Connection of CS8900 to MC68302
5.3 Design example: CS8900 inter-
face to MC68302
In this example the CS8900 is connected
to Motorola micro-controller MC68302.
Please refer to Figure 5.1 to check the
connection of control signals between
CS8900 and Motorola's micro-controller
MC68302.

5.3.1 Address Generation

The MC68302 has address decode gen-
eration logic internal to the micro-
controller. It generates chip select sig-
nals such as CS1*. In this example the
CS1* is used to access the CS8900 in IO
as well as in Memory mode. The behav-
ior of the CS1* signal from the
MC68302 is governed by values pro-
grammed in the CS1 base address regis-
74
CS8900 Technical Reference Manual
74F32
CS1*
R/W*
74F04
74F32
74F04
74F32
74F32
ter and the CS1 option register. For ex-
ample, if the CS1 base address register
is programmed as 3A01h, the CS1* will
have a base address of D00xxxh. The
CS1 operation register controls the ad-
dress range, number of wait states (to be
inserted automatically), etc. It is rec-
ommended that the CS8900 be assigned
8K of address space (0D00000h-
0D01FFFh). Memory mode of the
CS8900 is enabled with the memory
base address register with a value
001000h. The address line A12 sepa-
rates IO address space and memory ad-
dress space. When A12 is low, the
CS8900 is accessed in an IO mode and
when A12 is high, the CS8900 is ac-
cessed in memory mode.
MC68302 generates address 0D00300h,
the address seen by the CS8900 will be
00300h with one of the IO commands
(IOR* or IOW*) active. Similarly when
CS8900
SBHE*
SA0
SA [1:11]
SA12
SA[13:19]
MEMW*
IOW*
MEMR*
IOR*
INTRQ0
When the
AN83REV1