Cs8900 In Memory Mode; Dma Interface Of The Cs8900 - Cirrus Logic CRYSTAL LAN CS890 Technical Reference Manual

In an IO mode, the CS8900 uses 16
bytes of IO address space. The address
map for this mode is described in table
4.5 in the CS8900 datasheet.

5.1.3 CS8900 in memory mode

When the CS8900 is used in memory
mode, the CS8900 responds in the
memory address space of the ISA bus.
The CS8900 responds to a memory
mode access when
♦ The CHIPSEL* pin is active,
♦ Either of the bus memory command
lines (MEMR* or MEMW*) is ac-
tive,
♦ Both of the IO command lines (IOR*
and IOW*) are inactive,
♦ the address on bus signals SA[0:19]
matches the address in the CS8900's
Memory Base address register,
♦ MemoryE (Bit A) in the CS8900's
BusCTL (Register 17) is active and,
♦ Bus
signals AEN,
TEST*, SLEEP* and RESET are in-
active.
In memory mode, all the internal regis-
ters of the CS8900 can be accessed di-
rectly via memory reads/writes. Please
refer to table 4.1 in the CS8900 da-
tasheet for the memory address map.

5.1.4 DMA interface of the CS8900

The CS8900 can interface to an external
16-bit DMA channel for receive opera-
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CS8900 Technical Reference Manual
tions. A DMA-mode receive operation
can be selected by setting either
RxDMAOnly (bit 9) or AutoRxDMA
(bit 10) in the CS8900's RxCFG
(Register 3) register. The CS8900 will
request services of an external DMA af-
ter a receive frame is accepted by the
CS8900, completely received and stored
in on chip RAM of the CS8900. The
CS8900 generates a request for DMA
access (DRQx) signal when it has at
least one receive frame that can be trans-
ferred to the system memory. The ex-
ternal DMA channel should assert
DMACK* signal when it is ready to
transfer data. The DMA controller gen-
erates address for the system memory
and asserts the AEN signal.
DMACK* and AEN signals are asserted,
the CS8900 provides 16 bits of frame
data for every pulse of the IOR* signal.
Notice that the CS8900 ignores address
on the SA address lines for this opera-
tion. In this way the CS8900 supports
"direct mode" of operation of DMA. In
direct mode, the external DMA control-
ler generates addresses for the system
RAM, and generates the appropriate
control signals for the RAM and IO de-
REFRESH*,
vice. The data moves directly from the
IO device to the RAM. In the case of
the CS8900, the DMA controller gener-
ates a write signal for RAM and a read
signal for the CS8900. The data flows
directly from the CS8900 to the system
RAM. The direct mode of DMA opera-
tion is 100% more efficient than typical
read-followed-by-write DMA operation.
The length of time that the CS8900
holds the DRQ signal active depends
upon the DMABurst (bit B) bit of the
BusCTL (Register 17) register. If the
DMABurst is clear, the DRQ remains
When
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