Addressing The Cs8900: I/Omode , Memory Mode; I/O Mode; Memory Mode; Lower Memory Mode - Cirrus Logic CRYSTAL LAN CS890 Technical Reference Manual

2.3 Addressing the CS8900: I/O
mode, Memory mode
The CS8900, integrated Ethernet controller,
has 20 address pins that directly connect to
SA[19:0] of the ISA bus. The CS8900 has
an internal address comparator to compare
the ISA address with its base address regis-
ters.

2.3.1 I/O mode

In IO mode, the lower 16 bits of the ISA
address are compared with the address
stored in IO Base Address register (Packet
Page base + 020h).
match occurs and one of the IO command
(IOR* or IOW*) lines is active, the CS8900
responds to that IO access. The lower 4
bits of address lines are ignored by the ad-
dress comparator. This dictates that the
CS8900 must always be at a 16 byte ad-
dress boundary of the ISA IO address
space. The pin CHIPSEL* is ignored for an
IO mode access.
After RESET the CS8900 responds to IO
address 0300h. However, this condition
can be modified with use of an EEPROM
or by software. Immediately after a reset,
the CS8900 reads the EEPROM interfaced
to it. If the EEPROM has valid data (valid
start data and correct checksum), it will
read information stored in the EEPROM to
initialize its own registers including the IO
base address register. Please refer to sec-
tion 3.4 and 3.5 of CS8900 datasheet for
details about configuration with EEPROM
and programming of EEPROM.
CS8900 will always respond to valid IO
address (even if its memory mode is en-
abled).
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When an address
A
CS8900 Technical Reference Manual

2.3.2 Memory mode

In the memory mode, there are two options
where the CS8900 can be placed in the ISA
memory address map, lower memory
(below 1 Meg) or extended memory (above
1 Meg). The lower memory typically con-
sists of the conventional memory (up to
640K) and upper memory (640K to 1 Meg.
boundary). To access anything in extended
memory, the processor (386 and above) is
used in the "Enhanced Mode".
The CS8900 will respond to IO addresses
programmed in its IO Base Address Regis-
ter (Packet Page Base + 020h) even if
memory mode is enabled.
memory mode, first write a proper 20 bit
value to Memory Base Address register at
Packet page base + 02Ch & 02Eh. Then
set MemoryE (bit 0Ah) in the Bus CTL
register (Register 17) to one.
These operations can be performed either
by doing writes using IO mode accesses or
using an EEPROM as described in section
3.4 and 3.5 of the CS8900 datasheet. The
CS8900 will respond to an ISA memory
access, if the CHIPSEL* pin is active
(LOW), and the SA[19:0] match the value
stored in Memory Base Address Registers.
The lower 12 bits of the address lines are
always ignored. This dictates that the
CS8900 must always be placed at a 4K
boundary in the ISA memory address space.

2.3.2.1 Lower Memory mode

To use a CS8900 in the lower 1 Meg ad-
dress space, SMEMRD* and SMEMWR*
lines from the ISA bus are connected to
MEMR* and MEMW* pins of CS8900
respectively. The
To enable
SMEMRD* and
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