Read And Write Signals; Sbhe* Signal; Other Control Signals; Status Signals From Cs8900 - Cirrus Logic CRYSTAL LAN CS890 Technical Reference Manual

the MC68302 generates
0D01400h, the address seen by the
CS8900 will be 01400h with one of its
memory commands
MEMW*) active. For a MC68302, you
can also specify the number of wait
states that should be inserted automati-
cally when address space assigned to
CS1 is accessed. The number of wait
states used depends upon the clock input
to the MC68302. Please do a complete
timing analysis before defining wait
states.

5.3.2 Read and write signals

The combination of OR gates and an
inverter shown in Figure 1, generates IO
commands (IOR*, IOW*)
memory commands
MEMW*) for the CS8900. Since the
CS1* gates these signals, the IO or
memory commands are not generated
unless the address on the address bus is
stable. Further, for an access in memory
mode, an IO command is not active.

5.3.3 SBHE* signal

The CS8900 is a 16 bit device and it
should be used as a 16 bit device. How-
ever, after a hardware or software reset,
the CS8900 behaves as an 8 bit device.
Any transition on pin SBHE* places the
CS8900 into 16-bit mode. Further, for a
16-bit access, the SBHE* pin of the
CS8900 must be low. In the design ex-
ample, the CPU address line A0 is con-
nected to SBHE*. Before any access to
the CS8900, the design must guarantee
one transition on SBHE* pin.
AN83REV1
address
(MEMR* or
as well as
(MEMR*,
CS8900 Technical Reference Manual

5.3.4 Other control signals

All other control signals can be tied
HIGH or LOW. The signal REFRESH*,
TEST*, SLEEP*, AEN should be tied
inactive.

5.3.5 Status signals from CS8900

There are several status signals that are
output from the CS8900, such as IO-
CHRDY, IOCS16*, MCS16*, etc. In
the most embedded designs, they are not
needed. Those pins from the CS8900
should be left open.

5.4 Databus (SD[0:15]) Connection

All the internal registers of the CS8900
are 16 bit wide. For all the registers, bit
F of the register is access via SD15 and
bit 0 of register is accessed via SD0.
To be compatible with byte ordering
with ISA bus, the CS8900 provides the
bytes received from the Ethernet wire in
the following fashion. Assume that the
data received from the Ethernet wire is
01, 02, 03, 04, 05, ... where the 01 is the
first byte, 02 is the second byte and so
on. When the CS8900 transfers that
data to the host CPU, the data words are
read from the CS8900 as 0201, 0403,
etc. For certain microprocessor systems,
the designer may prefer to read the data
as 0102, 0304, etc. In such a case, the
databus connections to the CS8900 can
be altered by connecting the CPU
databus D[0:7] to the SD[8:15] pins of
the CS8900 and the CPU databus
D[8:15] to the SD[0:7] pins of the
CS8900. In such a case, make sure that
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