Introduction; Features - Epson S5U13705B00C User Manual

Isa bus evaluation board

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1 Introduction

S5U13705B00C Rev 1.0 Evaluation Board

Rev. 3.1

This manual describes the setup and operation of the S5U13705B00C Rev. 1.0 Evaluation

Board. Implemented using the S1D13705 Embedded Memory Color LCD Controller, the

S5U13705B00C board is designed for the 16-bit ISA bus environment. To accommodate

other bus architectures, the S5U13705B00C board also provides CPU/Bus interface

connectors.

For more information regarding the S1D13705, refer to the S1D13705 Hardware

Functional Specification, document number X27A-A-001-xx.

This document is updated as appropriate. Please check for the latest revision of this

document before beginning any development. The latest revision can be downloaded at

vdc.epson.com.

We appreciate your comments on our documentation. Please contact us via email at

vdc-documentation@ea.epson.com.

• 80-pin QFP14 package.

• SMT technology for all appropriate devices.

• 4/8-bit monochrome and color passive LCD panel support.

• 9/12-bit LCD TFT/D-TFD panel support.

• Selectable 3.3V or 5V LCD panel support.

• Oscillator support for CLKI (up to 50MHz with internal clock divider or 25MHz with

no internal clock divider).

• Embedded 80K byte SRAM display buffer for 1/2/4 bit-per-pixel (bpp), 2/4/16-level

gray shade display and 1/2/4/8 bpp, 2/4/16/256 level color display.

• Support for software and hardware power save modes.

• On-board adjustable LCD bias positive power supply (+23V to +40V).

• On-board adjustable LCD bias negative power supply (-23V to -14V).

• 16-bit ISA bus support.

• CPU/Bus interface header strips for non-ISA bus support.

Seiko Epson Corporation

Introduction

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