Decoding Logic; Clock Input Support - Epson S5U13705B00C User Manual

Technical Description

6.4 Decoding Logic

!CS = (Address >= ^hC0000) & (Address <= ^hDFFFF) & !ADDR & REFRESH & ENAB
# (Address1 >= ^hF00000) & (Address1 <= ^hF1FFFF) & ADDR & REFRESH & ENAB;
!MEMCS16 = (Address1 >= ^h0C0000) & (Address1 <= ^h0DFFFF) & !ADDR & !CS
# (Address1 >= ^hF00000) & (Address1 <= ^hF1FFFF) & ADDR & !CS;
!WE0 = (!CS & !ADDR & !SMEMW) # (!CS & ADDR & !MEMW);
!RD = (!CS & !ADDR & !SMEMR) # (!CS & ADDR & !MEMR);

6.5 Clock Input Support

14
When using the header strips to provide the bus interface observe the following:
• All signals on the ISA bus card edge must be isolated from the ISA bus (do not plug the
card into a computer). Power must be provided through the headers.
• U7, a PLD of type 22V10-15, is used to provide the S1D13705 CS# (pin 74) and other
decoding logic signals for ISA bus mode. For non-ISA applications, this functionality
must be provided externally. Remove the PAL from its socket to eliminate conflicts
driving S1D13705 control signals. Refer to Table 5-1: "Host Bus Interface Pin
Mapping" for connection details.
Note
When using a 3.3V host bus interface, IO V
(JP1) to the 2-3 position. Refer to Table 2-3: "Jumper Settings," on page 7.
All the required decode logic is provided through a PLD of type 22V10-15 (U7, socketed).
This PAL contains the following equations.
Note
ADDR = Switch S1-5 (see Table 2-1:, "Configuration DIP Switch Settings," on page 6).
The input clock (CLKI) frequency can be up to 50MHz for the S1D13705 if the internal
clock divide-by-2 mode is set. If the clock divider is not used, the maximum CLKI
frequency is 25MHz. There is no minimum input clock frequency.
A 25.0MHz oscillator (U2, socketed) is provided as the input clock source. However,
depending on the LCD resolution , desired frame rate, and power consumtion budget, a
lower frequency clock may be required.
Seiko Epson Corporation
must be set to 3.3V by setting jumper
DD
S5U13705B00C Rev 1.0 Evaluation Board
Rev. 3.1