Counter; Power Consumption - Measurement Computing PCI-DAS1602/16 User Manual

PCI-DAS1602/16 User's Guide

Counter

*Note: Pins 21, 24, and 25 are pulled to logic high via 10K resistors.
Counter type
Configuration
82C54A:
Counter 0 — ADC residual sample
counter.
Counter 1 — ADC pacer lower
divider
Counter 2 — ADC pacer upper
divider
82C54B:
Counter 0 — pretrigger mode
Counter 0 — non-pretrigger mode:
user counter 4
Counter 1 — DAC pacer lower
divider
Counter 2 — DAC pacer upper
divider
Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width high
Gate width low
Input high
Input low
Output high
Output low
Crystal oscillator frequency
Frequency accuracy

Power consumption

+5 V operating (A/D converting to FIFO)
Table 11. Counter specifications
82C54
Two 82C54 chips containing three 16-bit down counters each
Source: ADC Clock.
Gate: Programmable source.
Output: End-of-Acquisition interrupt.
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Output: Chained to Counter 2 Clock.
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Output: ADC Pacer clock (if software selected), available at user
connector.
Source: ADC Clock.
Gate: External trigger
Output: End-of-Acquisition interrupt.
Source: User input at 100pin connector or internal 10MHz (software
selectable)
Gate: User input at 100pin connector.
Output: Available at 100pin connector.
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Output: Chained to Counter 2 Clock.
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Output: DAC Pacer clock, available at user connector.
10 MHz max
30 ns min
50 ns min
50 ns min
50 ns min
2.0 volts min, 5.5 volts absolute max
0.8 volts max, -0.5 volts absolute min
3.0 volts min @ -2.5 mA
0.4 volts max @ 2.5 mA
10 MHz
50 ppm
Table 12. Power consumption specifications
2 A typical, 2.1 A max
25
Specifications