Connectors Description; Pin Signal - Seco Qseven Q7-C26 User Manual

3.2 Connectors description

3.2.1 CSI Camera Connector
CSI Camera Connector
Pin Signal Pin
1 +3.3V_RUN 19
2 +3.3V_RUN 20
3 MIPI_CSI0_D0+ 21
4 MIPI_CSI0_D0- 22
5 GND 23
6 MIPI_CSI0_D1+ 24
7 MIPI_CSI0_D1- 25
8 GND 26
9 MIPI_CSI0_D2+ 27
10 MIPI_CSI0_D2- 28
11 MIPI_CSI0_RST 29
12 HDMI_CSI1_LANE3+ 30
13 HDMI_CSI1_LANE3- 31
14 GND 32
15 MIPI_CSI0_CSI_CLK+ 33
16 MIPI_CSI0_CSI_CLK- 34
17 GND 35
18 MIPI_CSI0_I2C0_SCL 36
MIPI_CSI0_D2+/ MIPI_CSI0_D2-: CSI0 third input differential pair. It is managed by i.MX8 CSI0_D2 differential pair.
MIPI_CSI0_RST: CSI0 External camera module reset signal output. Managed by i.MX8 MIPI_CSI0_GPIO0 pin.
Q7-C26
Q7-C26 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0
NXP i.MX8 Processors include an Imaging Subsystem
CN3
capturing the incoming pixel data from multiple input
sources and storing them into the memory. The Imaging
Signal
Subsystem consists of the Imaging Sensor Interface (ISI),
MIPI_CSI0_I2C0_SDA
MJPEG Encoder and MJPEG Decoder. The pixel data for
the ISI can come from different image input sources, such
MIPI_CSI0_EN
as MIPI CSI and HDMI.
MIPI_CSI0_MCLK_OUT
The MIPI CSI subsystem of i.MX8 Processors handles the sensor/image input and process for
MIPI_CSI1_EN
CSI type input imaging devices. It consists of two MIPI-CSI interfaces that support up to 4 data
HDMI_CSI1_I2C0_SCL
lanes. In addition to this, in i.MX8 Processors there is a HDMI Receiver Subsystem capturing
image and sending it to the ISI via the Pixel link interface.
HDMI_CSI1_I2C0_SDA
In Q7-C26, there are two MIPI-CSI input interfaces, where the second interface can be
GND
configured via a multiplexer to become an HDMI Input interface.
HDMI_CSI1_LANE2+
In case two MIPI-CSI input interfaces are configured, the first one (MIPI-CSI0) is a MIPI-CSI with
HDMI_CSI1_LANE2-
4 data lanes and the second one (MIPI-CSI1) is a MIPI-CSI with 2 data lanes.
GND
When one MIPI-CSI and one HDMI input interfaces are configured, the MIPI-CISI has 3 data
HDMI_CSI1_LANE0+
lanes.
HDMI_CSI1_LANE0-
It is possible to access to the video input port through an FFC/FPC connector, type HIROSE
MIPI_CSI1_RST
p/n FH12A-36S-0.5SH(55) which is able to accept 36 poles 0.5mm pitch FFC cables.
HDMI_CSI1_LANE1+
The pinout of this connector is shown in the table on the left.
HDMI_CSI1_LANE1-
GND
MIPI_CSI0_D0+/ MIPI_CSI0_D0-: CSI0 first input differential pair. It is managed by i.MX8
CSI0_D0 differential pair.
CAM0_GPIO1
CAM1_GPIO1 / MIPI_CSI0_D1+/ MIPI_CSI0_D1-: CSI0 second input differential pair. It is managed by i.MX8
MIPI_CSI1_MCLK_OUT
CSI0_D1 differential pair.
Author: A.R - Reviewed by S.R. - Copyright © 2020 SECO S.p.A
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