Seco Qseven Q7-C26 User Manual page 33

Table of Contents

3.2.10

Audio interface signals

Q7-C26 module supports I2S audio format, thanks to native support offered by the processor to this audio codec standard.

Here following the signals related to I2S Audio interface:

I2S_WS: I2S Word Select Signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_RST#: I2S Codec Reset. Active Low signal Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_CLK: I2S Serial Data Clock signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_SDO: I2S Serial Data Out signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_SDI: I2S Serial Data In signal. Input to the module from the Carrier board, electrical level +3.3V_RUN.

All these signals have to be connected, on the Carrier Board, to an I2S Audio Codec. Please refer to the chosen Codec s Reference Design Guide for correct

implementation of audio section on the carrier board.

3.2.11

LVDS / eDP Flat Panel signals

All processors included in i.MX8 family include an LVDS Display Bridge (LDB) for connecting to an External LVDS Display Interface. The purpose of the LDB is to

support flow of synchronous RGB data to external display devices through the LVDS interface.

This allows to implement a Dual Channel or 2 x Single Channel 18- / 24-bit LVDS interface.

As a factory alternative, a Single Channel 18 / 24 bit LVDS and eDP interface can be implemented. In this case, HDMI / DP interface signals are not available.

EITHER the signals for primary channel are LVDS:

LVDS_A0+/LVDS_A0-: LVDS Primary Channel #0 differential data pair #0.

LVDS_A1+/LVDS_A1-: LVDS Primary Channel #0 differential data pair #1.

LVDS_A2+/LVDS_A2-: LVDS Primary Channel #0 differential data pair #2.

LVDS_A3+/LVDS_A3-: LVDS Primary Channel #0 differential data pair #3.

LVDS_A_CLK+/LVDS_A_CLK-: LVDS Primary Channel #0 differential clock.

OR the signals for primary channel are eDP:

eDP0_TX0+/ eDP0_TX0-: embedded DisplayPort Channel #0 differential data pair #0

eDP0_TX1+/ eDP0_TX1-: embedded DisplayPort Channel #0 differential data pair #1

eDP0_TX2+/ eDP0_TX2-: embedded DisplayPort Channel #0 differential data pair #2

eDP0_TX3+/ eDP0_TX3-: embedded DisplayPort Channel #0 differential data pair #3

Q7-C26