Seco Qseven Q7-C26 User Manual page 22

HDMI_CSI1_LANE3+/ HDMI_CSI1_LANE3-: it is CSI0 fourth input differential pair managed by i.MX8 CSI0_D3 differential pair in MIPI-CSI mode. When configured as
HDMI input, it is HDMI Clock input managed by i.MX8 HDMI_RX0_CLK differential pair.
MIPI_CSI0_CSI_CLK+ / MIPI_CSI0_CSI_CLK-: CSI0 Clock input differential pair. It is managed by i.MX8 MIPI_CSI0_CLK differential pair.
MIPI_CSI0_I2C0_SCL: CSI0 I2C Clock Control Signal. Managed by i.MX8 MIPI_CSI0_I2C0_SCL pin,
MIPI_CSI0_I2C0_SDA: CSI0 I2C Data Control Signal. Managed by i.MX8 MIPI_CSI0_I2C0_SDA pin,
MIPI_CSI0_EN: CSI0 Camera enable output signal. Managed by i.MX8 MIPI_CSI0_GPIO1 pin.
MIPI_CSI0_MCLK_OUT: CSI0 Camera Master Clock
however, to use camera modules with onboard crystal / oscillator, and avoid using this signal. Indeed, it could cause problems for EMI compliance requirements.
MIPI_CSI1_EN: CSI1 Camera enable output signal. Managed by i.MX8 MIPI_CSI1_GPIO1 pin. Only used when this interface is enabled.
HDMI_CSI1_I2C0_SCL: CSI1 I2C Clock Control Signal in MIPI-CSI mode. Managed by i.MX8 MIPI_CSI1_I2C0_SCL pin,
up resistor. When configured as HDMI input, it is Display Data Channel Data Signal. Managed by i.MX8 HDMI_RX0_DDC_SCL pin, electrical level +5V_RUN with a
-up resistor
HDMI_CSI1_I2C0_SDA: CSI1 I2C Data Control Signal in MIPI-CSI mode. Managed by i.MX8 MIPI_CSI1_I2C0_SDA pin,
up resistor. When configured as HDMI input, it is Display Data Channel Clock Signal. Managed by i.MX8 HDMI_RX0_DDC_SDA pin, electrical level +5V_RUN with a
-up resistor
HDMI_CSI1_LANE2+/ HDMI_CSI1_LANE2-: it is CSI1 Clock input differential pair. It is managed by i.MX8 MIPI_CSI1_CLK differential pair. When configured as HDMI
input, it is HDMI third lane input differential pair, managed by i.MX8 HDMI_RX0_D2 differential pair.
HDMI_CSI1_LANE0+/ HDMI_CSI1_LANE0-: it is CSI1 first input differential pair. It is managed by i.MX8 CSI1_D0 differential pair.. When configured as HDMI input, it
is HDMI first lane input differential pair, managed by i.MX8 HDMI_RX0_D0 differential pair.
MIPI_CSI1_RST: CSI1 External camera module reset signal output. Managed by i.MX8 MIPI_CSI1_GPIO0 pin. Only used when this interface is enabled
HDMI_CSI1_LANE1+/ HDMI_CSI1_LANE1-: it is CSI1 second input differential pair. It is managed by i.MX8 CSI1_D1 differential pair.. When configured as HDMI
input, it is HDMI second lane input differential pair, managed by i.MX8 HDMI_RX0_D1 differential pair.
CAM0_GPIO1: GPIO for Camera 0
CAM1_GPIO1: GPIO for Camera 1. It may be used as CSI1 Camera Master Clock
MIPI_CSI1_MCLK_OUT pin. It is suggested, however, to use camera modules with onboard crystal / oscillator, and avoid using this signal. Indeed, it could cause
problems for EMI compliance requirements.
Q7-C26
Q7-C26 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0
t is managed by i.MX8 MIPI_CSI0_MCLK_OUT pin. It is suggested,
Author: A.R - Reviewed by S.R. - Copyright © 2020 SECO S.p.A
-up resistor.
-up resistor
-
-
t is managed by i.MX8
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