Pci Express Interface Signals - Seco Qseven Q7-C26 User Manual

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3.2.6

PCI Express interface signals

The Q7-C26 module can offer two PCI Express x1 lane or one PCI Express x2 lanes , which are directly managed by i.MX8 processor (all versions).

PCI express Gen 3.0 (8Gbps) is supported.

Here following the signals involved in PCI express management

PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair

PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair

PCIE1_RX+/PCIE1_RX-: PCI Express lane #1, Receiving Input Differential pair

PCIE1_TX+/PCIE1_TX-: PCI Express lane #1, Transmitting Output Differential pair

PCIE_CLK_REF+/PCIE_CLK_REF-: PCI Express Reference Clock, Differential Pair. This clock is generated by an external Clock generator, type Renesas p/n

9FGV0241 present on module.

PCIE_RST#: Reset Signal that is sent from Qseven® Module to any PCI-e device available on the carrier board. It is a +3.3V_RUN active-low signal; it can be used

directly to drive externally a single RESET Signal. In case there is the need to supply Reset signal to multiple devices, it is recommended to provide for a buffer on the

carrier board.

PCIE_WAKE#: Wake up Signal that is asserted from any PCI-e device available on the carrier board to Qseven® Module. It is a 3V3_ALW active-low signal with a

-up resistor. Controlled by a STM32 MCU soldered onboard the Q7 module.

Q7-C26

Q7-C26 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0

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