Boot Data Register (0X7C) - Aceinna IMU383 Series User Manual

IMU383ZA Series User's Manual
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NOTE: Data Ready signal will be HIGH when device is BUSY and LOW when device available
for new transaction over SPI interface.
NOTE: Each command message includes 16-bit CRC which covers first 16 bit command word
and 32-bit data word.
9.2.4

Boot Data Register (0x7C)

The Boot Data register (0x7C) is dedicated to receiving fragments of application image one at a
time. The application image is split into N 256-byte fragments. Messages containing those
fragments are sent to the device sequentially and must include fragment number and CRC.
Fragment N corresponds to byte offset N*256 from start of binary application image. Once
received and verified the fragment gets buffered in CPU RAM. If required one can read
BOOT_STATUS register after sending each fragment to ensure that the fragment was received
successfully. This is done by checking bits "Last Operation status" and "CRC check status".
The next figure illustrates sending fragment of application image to the device over SPI interface:
nSS
CLK
MOSI
0xFC00
N/A
MISO
DRDY
NOTE: Data Ready signal will be HIGH when device is BUSY and LOW when device available
for new transaction over SPI interface.
NOTE: Status word will be sent back in second 16-bit word. It will reflect status of previous SPI
transaction execution.
NOTE: There should be delay at least 15 uS between fragment number word and data words.
NOTE: Application image will be padded for size to be even to 256 bytes.
Doc# 7430-1398-01
15 uS
Fragment #
Data (256 bytes)
(16 Bit)
STATUS
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CRC (2 bytes)
N/A
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