Spi Timing - Aceinna IMU383 Series User Manual

IMU383ZA Series User's Manual
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·
After releasing the reset line, the unit requires 300 msec (t
ready for use
·
Data should be read from the unit after the data-ready line is set active (low) (see Section
4.8.1)
Power-on
of master
Vcc
nRST held low during
master boot-up sequence
nRST
DR
nSS
4.9.2

SPI Timing

The timing requirements for the SPI are listed in Table 24 and illustrated in Figure 12 and Figure
13. In addition, the following operational constraints apply to the SPI communications:
·
The unit operates with CPOL = 1 (polarity) and CPHA = 1 (phase)
·
Data is transmitted 16-bits words, Most Significant Bit (MSB) first
Parameter
f
CL
SPI clock frequency
t Time between 16-bit bus cycles
DELAY
t nSS setup time prior to clocking data
SU,NSS
t
nSS hold time following clock signal
h,NSS
t Time after falling edge of previous clock-edge that MISO data-
V,MISO
bit is invalid
t Data input setup time prior to rising edge of clock
SU,MOSI
t Data input hold time following rising edge of clock
h,MOSI
Doc# 7430-1398-01
nRST pulled low
following power-on
nRST released after
system configured
t
Reset Delay
Figure 11 Startup Timing
Table 24 SPI Timing Requirements
Description
Downloaded From Oneyac.com
) before the system is
System Delay
Set nSS low to read data
when Data-Ready line is set
Value Units
1.2 MHz
(max)
15 (min) usec
133 nsec
133 nsec
25 nsec
5 nsec
4 nsec
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