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IMU383ZA Series User's Manual
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In polled-mode, the IMU383 transfers information from any register back to the master in two (or
3
more) SPI cycles
. In Burst-Mode, the IMU383 transfers predefined blocks of data in one
contiguous group of nine to twenty SPI cycles.
4.2.1
IMU383 SPI Port Polled-Mode Read
In polled-mode, data transfer begins when the SPI master sets the chip-select line (nSS) low and
clocks a 16-bit word, comprised of the register-address byte and a zero-byte, across the MOSI
line. For example, to request the unit's serial number, stored in register 0x58, the master sends
the command 0x5800. The unit returns information from this address across the MISO line
during the following 16 clock-cycles.
Subsequent SPI-master commands sent to the unit consist of either:
·
Sixteen zero-bits (0x0000) to complete the read of a single register.
·
The address of another register followed by a zero-byte. This permits back-to-back reads
of data-registers.
Single-Register Polled-Read
Figure 6 illustrates a polled-mode read of a single register (x-axis rate-sensor data), which is
composed of two bytes, starting at register address 0x04.
In this example, the SPI-master initiates a register read by clocking in the address followed by
0x00, i.e. 0x0400, via MOSI; this combination is referred to as a read-command
followed by 16 zero-bits to complete the SPI data-transfer cycle.
As the master transmits the read command over MOSI, the unit transmits information back over
MISO. In this transmission, the first data-word sent by the unit (as the read-command is sent)
consists of 16-bits of non-applicable data. The subsequent 16-bit message contains the x-axis
rate-sensor information (most significant byte followed by least-significant byte).
Figure 6 Single Register Read via Polled-Mode
4.2.2
IMU383 SPI Port Burst-Mode Read
In burst-mode, the unit returns predefined blocks of data in single groups, referred to as data-
packets, without the need to send multiple read commands. These groups vary from eight to ten
3
A SPI cycle consists of 16 clock cycles.
4
A read-command consists of an 8-bit register address and a zero byte (0x00).
Doc# 7430-1398-01
nSS
CLK
0x0400
0x0000
MOSI
N/A
X_RATE
MISO
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