Ad9863 Receive Section; Clocking - Analog Devices EVAL-ADF4602EB1Z Preliminary Technical Data

EVAL-ADF4602EB1Z
× ×
2 I R
=
OUTFSMAX DC
V
× +
diff
2 R R
DC
The common mode voltage V
I
= ×
OUTFSMAX
V R
CM DC
2
Using these equations, R is set to 120 Ω to give 1.2V common
DC
mode voltage, and R is set to 63Ω to give a 1V
L
input swing.
The TxPGA provides 20dB of simultaneous gain range for both
DACs and is controlled via the SPI port. The gain is in the range
of 10% to 100% I . Course gain controls are also available
OUTFSMAX
for each DAC output. Maximum settings (255) for both
TxPGA gain and course gain controls(Full gain) are
recommended for the evaluation board. This is because the
DAC output common mode voltage V
specific I . Varying the DAC gain will result in a different
OUTFSMAX
I and consequently a different V
OUTFSMAX
optimum for the ADF4602. With the DAC gain set permanently
at maximum, the transmit output power can be controlled via
the ADF4602 Tx power setting.
I/Q Mismatch Cancellation for Improved EVM
Performance
The TxDACs contain programmable fine gain controls and dc
offset controls. These can be used to compensate for
mismatches between I and Q channels which will aide in
suppressing LO feed-through, and improve the EVM
performance of the transmitter.
The 10-bit dc offset control of each DAC can be used
independently to provide up to +/- 12% I
either differential pin, thus allowing calibration of any system
offsets. The 5-bit fine gain control allows the I
DAC to be varied over a +/-4% range for compensation of any
DAC or system gain mismatches.

AD9863 RECEIVE SECTION

ADC Input
The AD9863 ADC input consists of a differential input
resistance of 2kΩ and a switched capacitor circuit. The input
can be self biased to mid-supply, or alternatively can be
programmed to accept an external DC bias. The ADF4602
receive baseband outputs can provide this external DC bias
(1.4V) and this is the preferred interface between the two
devices. The Rx receive settings files in Table 1 figure configure
the ADF4602 with 1.4V common mode output (programmable
1.2V or 1.4V), and the AD9863 input bias is disabled. On the
evaluation board, the ADF4602 receive baseband outputs are
thus connected directly to the AD9863 ADC inputs.
The ADC input full scale level is 2Vpk-pk differential.
×
R
= =
L
f ( I )
OUTFSMAX
L
is set by:
CM
differential
pk-pk
is designed with a
CM
which is not
CM
of offset to
OUTFSMAX
of each
OUTFSMAX
Digital Baseband Outputs
g ( R )
L The AD9863 provides two parallel 12-bit buses for the receive
I/Q data, or the data can be interleaved onto a single 12-bit bus.
See the AD9863 Baseband input/output section for more
details.
The baseband data is buffered and appears at connector J8. The
connector is designed to interface to the HSC-ADC-EVALB-
DC data acquisition board from Analog Devices. This board
can be used to capture blocks of digital data from the ADC for
offline processing. The Visual Analog software that
accompanies the data acquisition board analyzes the ADC SNR,
SINAD, SFDR and harmonic performance. Connector J10
should be connected to the bottom two rows of the data
acquisition board as shown in Figure 15.
Visual Analog software versions 1.2.3.0 and above support the
EVAL-ADF4602EB1Z evaluation board. The software is
included on the CD that accompanies the evaluation board.
Two setup files are also provided on the CD for. If using full
duplex (FD) mode, file
"AD9863_interleaved_data_FD_mode.vac" be used, for HD24
mode, file "AD9863_parallel_data_HD_24.vac" should be used.
Figure 16 shows a screenshot of the Visual Analog software in
use.
There are a number of possibilities for setting the sampling rate
of the ADC and the receive baseband output clocking – consult
the Clocking section for more details.
Note: The Visual Analog software and the EVAL-
ADF4602EB1Z software should not be operated simultaneously
on a single PC/laptop. This is due to the incompatibility of the
USB drivers. The Visual Analog software must be run on a
separate PC.

CLOCKING

ADF4602
The ADF4602 requires an external 26MHz reference input
signal. This is provided by on board VCTCXO U19. It is also
possible to apply an external 26MHz reference through SMA J1
– however care must be taken to ensure that the phase noise of
the external reference is excellent. An external reference with
poor phase noise will degrade the in-band phase noise of the
on-chip PLLs and result in poor transmitter and receiver EVM
performance.
The ADF4602 provides a buffered version of the 26MHz
reference, and also generates a 19.2MHz signal at pin 33
(CHIPCLOCK).
AD9863
The AD9863 has a very versatile clocking configuration with
many variables. Optimal power versus performance options can
be chosen to suit the users requirements. It is beyond the scope
of this document to discuss the many possible configurations in
detail, but the default evaluation board configuration is
Rev. PrC | Page 12 of 37
Preliminary Technical Data